Home

The project is about design, implementation and testing of a 16-bit multi-cycle RISC processor. Each instruction is of 16-bit (2 bytes) and passes through five cycles (max) IF, ID, EX, MEMR and WB similar to the standard MIPS Processor.

• Cycle-1 IF: Instruction Fetch
• Cycle-2 ID: Instruction Decode
• Cycle-3 EX: Execute
• Cycle-4 MEM: Memory operation (data memory)
• Cycle-5 WB: Write Back

---

The processor implements the following instructions.

Instruction	Cycles	Type of Addressing	OPCODE	~	~	~
ADD	4	Register	1000	Reg. No. 4-bit (Rd)	Reg. No. 4-bit (Rs)	Reg. No. 4-bit (Rt)
ADDI (sign ex)	4	Immediate	1001	Reg. No. 4-bit (Rd)	8-bit Data
ADDZ (zero ex)	4	Immediate	1010	Reg. No. 4-bit (Rd)	8-bit Data
SUB	4	Register	1100	Reg. No. 4-bit (Rd)	Reg. No. 4-bit (Rs)	Reg. No. 4-bit (Rt)
SUBI (sign ex)	4	Immediate	1101	Reg. No. 4-bit (Rd)	8-bit Data
SUBZ (zero ex)	4	Immediate	1110	Reg. No. 4-bit (Rd)	8-bit Data
SLL	4	Immediate	0000	Reg. No. 4-bit	4-bit Data	0001 (FUNC)
SRL	4	Immediate	0000	Reg. No. 4-bit	4-bit Data	0010 (FUNC)
SRA	4	Immediate	0000	Reg. No. 4-bit	4-bit Data	0010 (FUNC)
NAN	4	Register	1011	Reg. No. 4-bit (Rd)	Reg. No. 4-bit (Rs)	Reg. No. 4-bit (Rt)
OR	4	Register	1111	Reg. No. 4-bit (Rd)	Reg. No. 4-bit (Rs)	Reg. No. 4-bit (Rt)
NANI (sign ex)	4	Immediate	0111	Reg. No. 4-bit (Rd)	8-bit Data
ORI (sign ex)	4	Immediate	0110	Reg. No. 4-bit (Rd)	8-bit Data
BEQ	3	Register	0100	Reg. No. 4-bit (RTarget)	Reg. No. 4-bit (RA)	Reg. No. 4-bit (RB)
BNE	3	Register	0101	Reg. No. 4-bit (RTarget)	Reg. No. 4-bit (RA)	Reg. No. 4-bit (RB)
JMP	3	Immediate	0011	12-bit Address PC Relative
LW	5	Immediate	0001	Reg. No. 2-bit (RD)	Reg. No. 2-bit (RP)	8-bit Data
SW	4	Immediate	0010	Reg. No. 2-bit (RD)	Reg. No. 2-bit (RP)	8-bit Data

Remark: RD can be one among R12, R13, R14 and R15 and hence the upper 2-bits (11) of the register id are not specified. RP (pointer) can be one among R8, R9, R10 and R11 only, hence upper two bits (10) are not specified.