Add uid file needed for ethernet

copied over files, not modified properly yet

Squashing lots of define errors to get ethernet.c working

quick path rename

Fix STM32_EMAC_BASE (and ICACHE/DCACHE Bases). Enable ETH, ETHTX, and ETHRX with CONFIG_STM32H5_ETHMAC (like H7 does).

Fixed stm32_get_uniqueid

Previously, an exception occurred as a result of calling this function. The problem turned out to be this line: uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i);. Dereferencing a 32-bit register as a 8-bit register seemed to be causing this issue. I think this function is better anyway, fewer register accesses and loop iterations.

Turn on SBS peripheral when using Ethernet

The SBS peripheral is required to be turned on because the ETH_SEL_PHY bits need to be set. Without turning this on, RMII mode is not possible. MII may not work either.

Style Updates

arch/arm/include/stm32h5/chip.h

@@ -103,4 +103,10 @@
 #define NVIC_SYSH_PRIORITY_MAX     0x00 /* Zero is maximum priority */
 #define NVIC_SYSH_PRIORITY_STEP    0x10 /* Four bits of interrupt priority used */
 
+#if defined(CONFIG_STM32H5_HAVE_ETHERNET)
+#  define STM32H5_NETHERNET             1   /* Ethernet MAC */
+#else
+#  define STM32H5_NETHERNET               0   /* No Ethernet MAC */
+#endif
+
 #endif /* __ARCH_ARM_INCLUDE_STM32H5_CHIP_H */

arch/arm/src/stm32h5/Make.defs

@@ -31,12 +31,10 @@ include armv8-m/Make.defs
 
 # Required STM32H5 files
 
-CHIP_ASRCS  =
-CHIP_CSRCS  = stm32_gpio.c
-CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c
-CHIP_CSRCS += stm32_serial.c stm32_start.c
-CHIP_CSRCS += stm32_pwr.c stm32_timerisr.c
+CHIP_CSRCS += stm32_gpio.c stm32_irq.c stm32_lowputc.c stm32_rcc.c
+CHIP_CSRCS += stm32_serial.c stm32_start.c stm32_pwr.c stm32_timerisr.c
 CHIP_CSRCS += stm32_lse.c stm32_lsi.c
+CHIP_CSRCS += stm32_uid.c stm32_ethernet.c
 
 ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
 CHIP_CSRCS += stm32_idle.c

arch/arm/src/stm32h5/chip.h

@@ -50,4 +50,12 @@
 
 #define ARMV8M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS
 
+/* Cache line sizes set in line with ST document RM0481 Rev 2.
+ * DCACHE implementation, pg 284, Table 93
+ * ICACHE implementation, pg 367, Table 85.
+ */
+
+#define ARMV8M_ICACHE_LINESIZE 16   /* 16 bytes */
+#define ARMV8M_DCACHE_LINESIZE 16   /* 16 bytes */
+
 #endif /* __ARCH_ARM_SRC_STM32H5_CHIP_H */

arch/arm/src/stm32h5/hardware/stm32_sbs.h

@@ -93,8 +93,8 @@
 #define SBS_PMCR_PB9_FMP  (1 << 19) /* Fast-mode Plus on PB9*/
 
 #define SBS_PMCR_ETH_SEL_PHY_SHIFT           (21) /* Bits 23-21 Ethernet PHY interface selection */
-#define SBS_PMCR_ETH_SEL_PHY_MASK            (0b111 << SBS_ETH_SEL_PHY_SHIFT)
-#  define SBS_PMCR_ETH_SEL_PHY_GMII_OR_MII   (0 << SBS_ETH_SEL_PHY_SHIFT)
-#  define SBS_PMCR_ETH_SEL_PHY_RMII          (4 << SBS_ETH_SEL_PHY_SHIFT)
+#define SBS_PMCR_ETH_SEL_PHY_MASK            (0b111 << SBS_PMCR_ETH_SEL_PHY_SHIFT)
+#  define SBS_PMCR_ETH_SEL_PHY_GMII_OR_MII   (0 << SBS_PMCR_ETH_SEL_PHY_SHIFT)
+#  define SBS_PMCR_ETH_SEL_PHY_RMII          (4 << SBS_PMCR_ETH_SEL_PHY_SHIFT)
 
 #endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_SBS_H */