fix pylint

bat52 · Oct 25, 2024 · ca8a72a · ca8a72a
1 parent 539dd0f
commit ca8a72a
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/cheap_pie/cheap_pie_core/cbitfield.py b/src/cheap_pie/cheap_pie_core/cbitfield.py
@@ -144,7 +144,7 @@ def getbit(self, regval=None, echo=False, as_signed=False):
         #
         return fieldval
 
-    def setbit(self, fieldval=0, echo=False, writeback=True, 
+    def setbit(self, fieldval=0, echo=False, writeback=True,
                regval=None, verify=True):  # pylint: disable=W1113, R0913
         """ function display(self,regval)
         # displays value of a bitfield from a register value