wip

cranelift/codegen/src/isa/s390x/lower.isle

@@ -3844,6 +3844,80 @@
         (add_logical_mem_zext32_with_flags_paired ty y (sink_uload32 x))
         (trap_if_impl (mask_as_cond 3) tc)))
 
+;;;; Rules for `uadd_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule 0 (lower (has_type (fits_in_64 ty) (uadd_overflow x y)))
+  (let ((sum XReg (add_logical_mem_with_flags_paired ty x y))
+        (one XReg (imm $I8 1))
+        (overflow XReg (gen_select_xreg (mask_as_cond 3) one (zero_reg))))
+    (output_pair
+         (value_reg sum)
+         (value_reg overflow_flag))))
+
+(rule 1 (lower (has_type (fits_in_64 ty) (uadd_overflow x (sinkable_uload32 y))))
+  (let ((sum XReg (add_logical_mem_zext32_with_flags_paired ty x (sink_uload32 y)))
+        (one XReg (imm $I8 1))
+        (overflow XReg (gen_select_xreg (mask_as_cond 3) one (zero_reg))))
+    (output_pair
+         (value_reg sum)
+         (value_reg overflow))))
+
+(rule 2 (lower (has_type (fits_in_64 ty) (uadd_overflow x (sinkable_load_32_64 y))))
+  (let ((sum XReg (add_logical_mem_with_flags_paired ty x (sink_load y)))
+        (one XReg (imm $I8 1))
+        (overflow XReg (gen_select_xreg (mask_as_cond 3) one (zero_reg))))
+    (output_pair
+         (value_reg sum)
+         (value_reg overflow))))
+
+(rule 3 (lower (has_type (fits_in_64 ty) (uadd_overflow x (u32_from_value y))))
+  (let ((sum XReg (add_logical_zimm32_with_flags_paired ty x y))
+        (one XReg (imm $I8 1))
+        (overflow XReg (gen_select_xreg (mask_as_cond 3) one (zero_reg))))
+    (output_pair
+         (value_reg sum)
+         (value_reg overflow))))
+
+(rule 4 (lower (has_type (fits_in_64 ty) (uadd_overflow x (zext32_value y))))
+  (let ((sum XReg (add_logical_reg_zext32_with_flags_paired ty x y))
+        (one XReg (imm $I8 1))
+        (overflow XReg (gen_select_xreg (mask_as_cond 3) one (zero_reg))))
+    (output_pair
+         (value_reg sum)
+         (value_reg overflow))))
+
+(rule 5 (lower (has_type (fits_in_64 ty) (uadd_overflow (sinkable_uload32 x) y)))
+  (let ((sum XReg (add_logical_mem_zext32_with_flags_paired ty y (sink_uload32 x)))
+        (one XReg (imm $I8 1))
+        (overflow XReg (gen_select_xreg (mask_as_cond 3) one (zero_reg))))
+    (output_pair
+         (value_reg sum)
+         (value_reg overflow))))
+
+(rule 6 (lower (has_type (fits_in_64 ty) (uadd_overflow (sinkable_load_32_64 x) y)))
+  (let ((sum XReg (add_logical_mem_with_flags_paired ty y (sink_load x)))
+        (one XReg (imm $I8 1))
+        (overflow XReg (gen_select_xreg (mask_as_cond 3) one (zero_reg))))
+    (output_pair
+         (value_reg sum)
+         (value_reg overflow))))
+
+(rule 7 (lower (has_type (fits_in_64 ty) (uadd_overflow (u32_from_value x) y)))
+  (let ((sum XReg (add_logical_zimm32_with_flags_paired ty y x))
+        (one XReg (imm $I8 1))
+        (overflow XReg (gen_select_xreg (mask_as_cond 3) one (zero_reg))))
+    (output_pair
+         (value_reg sum)
+         (value_reg overflow))))
+
+(rule 8 (lower (has_type (fits_in_64 ty) (uadd_overflow (zext32_value x) y)))
+  (let ((sum XReg (add_logical_reg_zext32_with_flags_paired ty y x))
+        (one XReg (imm $I8 1))
+        (overflow XReg (gen_select_xreg (mask_as_cond 3) one (zero_reg))))
+    (output_pair
+         (value_reg sum)
+         (value_reg overflow))))
+
 ;;;; Rules for `return` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (rule (lower (return args))