staff update from: ece4750-tut4-verilog-0.0-350-gde03c8c

bzl3 · Aug 26, 2016 · dce15f8 · dce15f8
1 parent 66edc16
commit dce15f8
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Showing 7 changed files with 12 additions and 8 deletions.
diff --git a/sim/tut4_verilog/gcd/gcd-sim b/sim/tut4_verilog/gcd/gcd-sim
@@ -42,7 +42,7 @@ from GcdUnitFL      import GcdUnitFL
 from GcdUnitCL      import GcdUnitCL
 from GcdUnitRTL     import GcdUnitRTL
 
-from GcdUnitFL_test import TestHarness
+from test.GcdUnitFL_test import TestHarness
 
 #-------------------------------------------------------------------------
 # Command line processing

diff --git a/sim/tut4_verilog/gcd/GcdUnitCL_test.py → sim/tut4_verilog/gcd/test/GcdUnitCL_test.py b/sim/tut4_verilog/gcd/GcdUnitCL_test.py → sim/tut4_verilog/gcd/test/GcdUnitCL_test.py
@@ -6,7 +6,8 @@
 
 from pymtl      import *
 from pclib.test import run_sim
-from GcdUnitCL  import gcd, GcdUnitCL
+
+from tut4_verilog.gcd.GcdUnitCL  import gcd, GcdUnitCL
 
 # Reuse tests from FL model
 

diff --git a/sim/tut4_verilog/gcd/GcdUnitFL_test.py → sim/tut4_verilog/gcd/test/GcdUnitFL_test.py b/sim/tut4_verilog/gcd/GcdUnitFL_test.py → sim/tut4_verilog/gcd/test/GcdUnitFL_test.py
@@ -12,8 +12,8 @@
 from pclib.test import mk_test_case_table, run_sim
 from pclib.test import TestSource, TestSink
 
-from GcdUnitFL  import GcdUnitFL
-from GcdUnitMsg import GcdUnitReqMsg
+from tut4_verilog.gcd.GcdUnitMsg import GcdUnitReqMsg
+from tut4_verilog.gcd.GcdUnitFL  import GcdUnitFL
 
 #-------------------------------------------------------------------------
 # TestHarness

diff --git a/sim/tut4_verilog/gcd/GcdUnitMsg_test.py → sim/tut4_verilog/gcd/test/GcdUnitMsg_test.py b/sim/tut4_verilog/gcd/GcdUnitMsg_test.py → sim/tut4_verilog/gcd/test/GcdUnitMsg_test.py
@@ -4,7 +4,8 @@
 # Test suite for the GCD unit message
 
 from pymtl      import *
-from GcdUnitMsg import GcdUnitReqMsg
+
+from tut4_verilog.gcd.GcdUnitMsg import GcdUnitReqMsg
 
 #-------------------------------------------------------------------------
 # test_fields

diff --git a/sim/tut4_verilog/gcd/GcdUnitRTL_test.py → sim/tut4_verilog/gcd/test/GcdUnitRTL_test.py b/sim/tut4_verilog/gcd/GcdUnitRTL_test.py → sim/tut4_verilog/gcd/test/GcdUnitRTL_test.py
@@ -6,7 +6,8 @@
 
 from pymtl      import *
 from pclib.test import run_sim
-from GcdUnitRTL import GcdUnitRTL
+
+from tut4_verilog.gcd.GcdUnitRTL import GcdUnitRTL
 
 # Reuse tests from FL model
 

diff --git a/sim/tut4_verilog/gcd/test/__init__.py b/sim/tut4_verilog/gcd/test/__init__.py
diff --git a/sim/tut4_verilog/gcd/gcd_sim_test.py → sim/tut4_verilog/gcd/test/gcd_sim_test.py b/sim/tut4_verilog/gcd/gcd_sim_test.py → sim/tut4_verilog/gcd/test/gcd_sim_test.py
@@ -17,8 +17,9 @@ def test( impl, input_, test_verilog ):
 
   # Get path to simulator script
 
-  sim_dir = os.path.dirname( os.path.abspath( __file__ ) )
-  sim     = sim_dir + os.path.sep + 'gcd-sim'
+  test_dir = os.path.dirname( os.path.abspath( __file__ ) )
+  sim_dir  = os.path.dirname( test_dir )
+  sim      = sim_dir + os.path.sep + 'gcd-sim'
 
   # Command