[yxi] Rename calyx-axi-wrapper clock signal to ap_clk
#2386
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…og wrapper backwards compatability (i.e in gen_xo.tcl)
nathanielnrn
changed the title
ap_clkap_clk
rachitnigam
reviewed
Jan 24, 2025
| @@ -133,8 +133,8 @@ component m_read_channel(ARESETn: 1, RVALID: 1, RLAST: 1, RDATA: 32, RRESP: 2) - | |||
| n_RLAST = std_reg(1); | |||
| read_data_reg = std_reg(32); | |||
| bt_reg = std_reg(1); | |||
| curr_addr_internal_mem_incr = std_add(3); | |||
| curr_addr_axi_incr = std_add(64); | |||
| curr_addr_internal_mem_incr_1_1 = std_add(3); | |||
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Why did these names start getting changed?
rachitnigam
approved these changes
Jan 24, 2025
|
Looks like the new numbers are a result of #2152. Not sure why these tests weren't caught there? That said, merging. |
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Another PR whittling down the changes present in #2267.
This PR changes the toplevel clock signal from
clktoap_clk. This should allow us to reuse the existinggen_xo.tcland maintain backwards compatibility with the old verilog-axi-wrapper, without requiring a distinction between the two in thegen_xo.tclfile.Also fixes a bsd vs gnu
sedsyntax error. The new command should work on both.(bsd sed require terminating commands to end with a
;, gnu does not)I'll also note that this PR touches a bunch of runt cocotb tests in
tests/axi. I'm aware that there is a desire to get rid of large snapshots as they tend to get ignored. For now this setup is the best thing I have to make sure breaking changes aren't introduced to either axi-wrapper, so choosing to update them for now.