Bump libs and reformat. Cleanup gpio parameter

.mill-version

@@ -1 +1 @@
-0.11.1
+0.11.6

.scalafmt.conf

@@ -1,4 +1,4 @@
-version = 3.7.11
+version = 3.7.15
 
 runner.dialect = scala213
 maxColumn = 120

build.sc

@@ -6,12 +6,12 @@ import $ivy.`com.carlosedp::mill-aliases::0.4.1`
 import com.carlosedp.aliases._
 
 object versions {
-  val scala          = "2.13.10"
-  val chisel         = "5.0.0"
-  val chiseltest     = "5.0.1"
-  val scalatest      = "3.2.16"
+  val scala          = "2.13.12"
+  val chisel         = "5.1.0"
+  val chiseltest     = "5.0.2"
+  val scalatest      = "3.2.17"
   val riscvassembler = "1.9.1"
-  val mainargs       = "0.5.1"
+  val mainargs       = "0.5.4"
 }
 
 trait BaseProject extends ScalaModule with ScalafixModule with ScalafmtModule {

chiselv/src/GPIO.scala

@@ -59,28 +59,28 @@ class GPIOInOut(numGPIO: Int) extends BlackBox with HasBlackBoxInline {
   })
   setInline(
     "GPIOInOut.v",
-    s"""// This module is inspired by Lucas Teske's Riscow digital port
-       |// https://github.com/racerxdl/riskow/blob/main/devices/digital_port.v
-       |//
-       |module GPIOInOut #(parameter NUMGPIO=$numGPIO) (
-       |  inout   [NUMGPIO-1:0] dataIO,
-       |  input   [NUMGPIO-1:0] dataIn,
-       |  output  [NUMGPIO-1:0] dataOut,
-       |  input   [NUMGPIO-1:0] dir);
-       |
-       |  generate
-       |    genvar idx;
-       |    for(idx = 0; idx < NUMGPIO; idx = idx+1) begin: register
-       |      `ifdef SIMULATION
-       |      assign dataIO[idx] = dir[idx] ? dataIn[idx] : 1'b0;
-       |      `else
-       |      assign dataIO [idx]= dir[idx] ? dataIn[idx] : 1'bZ;
-       |      `endif
-       |     end
-       |  endgenerate
-       |  assign dataOut = dataIO;
-       |
-       |endmodule
-       |""".stripMargin,
+    s"""|// This module is inspired by Lucas Teske's Riscow digital port
+        |// https://github.com/racerxdl/riskow/blob/main/devices/digital_port.v
+        |//
+        |module GPIOInOut (
+        |  inout   [${numGPIO - 1}:0] dataIO,
+        |  input   [${numGPIO - 1}:0] dataIn,
+        |  output  [${numGPIO - 1}:0] dataOut,
+        |  input   [${numGPIO - 1}:0] dir);
+        |
+        |  generate
+        |    genvar idx;
+        |    for(idx = 0; idx < $numGPIO; idx = idx+1) begin: register
+        |      `ifdef SIMULATION
+        |      assign dataIO[idx] = dir[idx] ? dataIn[idx] : 1'b0;
+        |      `else
+        |      assign dataIO [idx]= dir[idx] ? dataIn[idx] : 1'bZ;
+        |      `endif
+        |     end
+        |  endgenerate
+        |  assign dataOut = dataIO;
+        |
+        |endmodule
+        |""".stripMargin,
   )
 }

chiselv/src/Toplevel.scala

@@ -73,6 +73,10 @@ object Toplevel {
         "--lower-memories",
         // Avoids "unexpected TOK_AUTOMATIC" errors in Yosys. Ref. https://github.com/llvm/circt/issues/4751
         "--lowering-options=disallowLocalVariables,disallowPackedArrays",
+        // Splits the generated Verilog into multiple files
+        "--split-verilog",
+        // Generates the Verilog files in the specified directory
+        "-o=./generated",
       ),
     )
 

gcc/helloUART/main.c

@@ -34,6 +34,7 @@ int main(void)
   header();
   // Print the banner
   printf(logocv);
+  printf("This demo prints back to the console all typed characters when hit <enter>.\n");
   printf("> ");
   char data[128];
   while (1)