New verification framework

[sequencer]

The basic verification idea of T1 IP is based on the online difftest. However when we are getting bigger and bigger, verification becomes a new problem, which we need to think about in a new way:

• Does online difftest really necessary?
• Answer is NO. Basically online difftest has no difference between offline. It just stop verification at early as possible, but does this really necessary? I don't think so.
• difftest only helps for those lazy guys don't wanna to re-implement SVA for each instructions.
• What's the interface between RTL and DV?
• Originally we use DPI to probe each signals from designs.
• But problem is, when we have different configurations, DPI call is different. C codegen is a nightmare.

Thus what we are looking for is a decoupled verification framework:

• There are two Verification frameworks to provide trade-off among: simulation performance, verification target, and delivery.
  • IP Level: forcing on the vector performance, avoiding and overhead from scalar part, it should skip the scalar execution with emulating by spike. The DPI input is Scalar->Vector IO and Memory IO. This signals are driven by DPI.
  • SoC Level: forcing on the Tile-level verification with Rocket as scalar code, it will fully test the performance of the vector tile. The interface is the front-pront for ITCM and DTCM and all vector memory ports

TBD, too tired.