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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 [email protected]

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

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  1. chisel chisel Public

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Repositories

Showing 10 of 109 repositories
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 94 Apache-2.0 44 103 57 Updated Nov 17, 2024
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 3,995 Apache-2.0 597 313 (1 issue needs help) 170 Updated Nov 17, 2024
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 119 Apache-2.0 22 16 23 Updated Nov 17, 2024
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl’s past year of commit activity
    SystemVerilog 75 Apache-2.0 38 70 11 Updated Nov 17, 2024
  • sv-tests-results Public

    Output of the sv-tests runs.

    chipsalliance/sv-tests-results’s past year of commit activity
    HTML 5 1 0 0 Updated Nov 17, 2024
  • dromajo Public

    RISC-V RV64GC emulator designed for RTL co-simulation

    chipsalliance/dromajo’s past year of commit activity
    C++ 216 Apache-2.0 63 18 6 Updated Nov 16, 2024
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    chipsalliance/caliptra-ss’s past year of commit activity
    SystemVerilog 8 Apache-2.0 2 11 1 Updated Nov 16, 2024
  • adams-bridge Public

    Post-Quantum Cryptography IP Core (Crystals-Dilithium)

    chipsalliance/adams-bridge’s past year of commit activity
    SystemVerilog 9 Apache-2.0 1 0 0 Updated Nov 16, 2024
  • firrtl-spec Public

    The specification for the FIRRTL language

    chipsalliance/firrtl-spec’s past year of commit activity
    TeX 45 28 23 18 Updated Nov 15, 2024
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    chipsalliance/sv-tests’s past year of commit activity
    SystemVerilog 297 ISC 75 45 (5 issues need help) 21 Updated Nov 16, 2024
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