CHIPS Alliance

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109 repositories

chisel-nix
Public
Nix template for the chisel-based industrial designing flows.
Nix
•5•35•2•1•Updated Mar 10, 2025Mar 10, 2025
chisel
Public
Chisel: A Modern Hardware Design Language
chip-generator chisel rtl chisel3 firrtl scala verilog
Scala
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Apache License 2.0
•618•4.2k•324•156•Updated Mar 10, 2025Mar 10, 2025
synlig
Public
SystemVerilog synthesis tool
Verilog
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Apache License 2.0
•24•180•69•12•Updated Mar 10, 2025Mar 10, 2025
caliptra-mcu-sw
Public
Caliptra MCU Software
Rust
•
Apache License 2.0
•2•9•12•3•Updated Mar 10, 2025Mar 10, 2025
sv-tests-results
Public
Output of the sv-tests runs.
HTML
•3•5•0•0•Updated Mar 10, 2025Mar 10, 2025
Caliptra
Public
Caliptra IP and firmware for integrated Root of Trust block
Apache License 2.0
•39•266•37•6•Updated Mar 10, 2025Mar 10, 2025
verilator
Public
Verilator open-source SystemVerilog simulator and lint system
C++
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GNU Lesser General Public License v3.0
•637•35•0•1•Updated Mar 9, 2025Mar 9, 2025
caliptra-sw
Public
Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test
Rust
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Apache License 2.0
•51•103•116•53•Updated Mar 8, 2025Mar 8, 2025
UHDM
Public
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
vpi-api serialization listener systemverilog ieee-standard vpi-interface
C++
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Apache License 2.0
•41•210•16•0•Updated Mar 8, 2025Mar 8, 2025
sv-tests
Public
Test suite designed to check compliance with the SystemVerilog standard.
rtl verilog systemverilog hdl compliance-testing symbiflow
SystemVerilog
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ISC License
•77•308•47•30•Updated Mar 7, 2025Mar 7, 2025
caliptra-ss
Public
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
security rot ocp root-of-trust caliptra opencomputeproject
SystemVerilog
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Apache License 2.0
•8•12•32•5•Updated Mar 7, 2025Mar 7, 2025
Cores-VeeR-EL2
Public
VeeR EL2 Core
fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital
SystemVerilog
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Apache License 2.0
•79•266•19•0•Updated Mar 7, 2025Mar 7, 2025
adams-bridge
Public
Post-Quantum Cryptography IP Core (Crystals-Dilithium)
cryptography digital-signature lattice pqc ml-dsa-87
SystemVerilog
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Apache License 2.0
•3•14•11•1•Updated Mar 7, 2025Mar 7, 2025
caliptra-rtl
Public
HW Design Collateral for Caliptra RoT IP
SystemVerilog
•
Apache License 2.0
•45•84•85•10•Updated Mar 7, 2025Mar 7, 2025
rocket-chip
Public
Rocket Chip Generator
chisel scala rocket-chip chip-generator riscv rtl
Scala
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Other
•1.2k•3.4k•237•65•Updated Mar 7, 2025Mar 7, 2025
t1
Public
Scala
•
Apache License 2.0
•33•255•20•28•Updated Mar 7, 2025Mar 7, 2025
caliptra-dpe
Public
High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs
Rust
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Apache License 2.0
•24•15•11•7•Updated Mar 6, 2025Mar 6, 2025
Surelog
Public
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
parser linter preprocessor antlr verilog python-api systemverilog uvm elaboration vpi
C++
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Apache License 2.0
•69•382•52•0•Updated Mar 6, 2025Mar 6, 2025
chips-alliance-website
Public
SCSS
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MIT License
•5•3•8•8•Updated Mar 5, 2025Mar 5, 2025
i3c-core
Public
SystemVerilog
•
Apache License 2.0
•5•16•9•0•Updated Mar 4, 2025Mar 4, 2025
synlig-logs
Public
SystemVerilog
•0•0•0•0•Updated Mar 3, 2025Mar 3, 2025
firrtl-spec
Public
The specification for the FIRRTL language
TeX
•30•51•25•16•Updated Mar 1, 2025Mar 1, 2025
tac
Public
CHIPS Alliance Technical Advisory Council
Apache License 2.0
•23•6•17•2•Updated Feb 27, 2025Feb 27, 2025
veer-el2-dashboard
Public
HTML
•2•0•0•0•Updated Feb 25, 2025Feb 25, 2025
homebrew-verible
Public
Ruby
•
Apache License 2.0
•8•18•0•0•Updated Feb 23, 2025Feb 23, 2025
chisel-interface
Public
The 'missing header' for Chisel
Scala
•2•18•0•0•Updated Feb 19, 2025Feb 19, 2025
verible
Public
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
productivity analysis style-linter language-server-protocol syntax-tree lexer yacc systemverilog hacktoberfest lsp-server
C++
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Other
•226•1.5k•493•21•Updated Feb 17, 2025Feb 17, 2025
rocket-pcblib
Public
Apache License 2.0
•0•1•0•0•Updated Feb 10, 2025Feb 10, 2025
riscv-dv
Public
Random instruction generator for RISC-V processor verification
Python
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Apache License 2.0
•334•1.1k•120•15•Updated Feb 7, 2025Feb 7, 2025
riscv-vector-tests
Public
Unit tests generator for RVV 1.0
generator spike riscv testsuite rvv
Go
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Apache License 2.0
•26•77•6•1•Updated Feb 6, 2025Feb 6, 2025