Fix GH-100: Incorrect stack alignment with VAR on aarch64

sp register must be always 16-bytes aligned
dstogov · Jan 20, 2025 · 745006f · 745006f
1 parent 4942279
commit 745006f
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Showing 4 changed files with 37 additions and 10 deletions.
diff --git a/ir_aarch64.dasc b/ir_aarch64.dasc
@@ -925,7 +925,7 @@ binop_fp:
 			if (ctx->flags & IR_FUNCTION) {
 				ctx->flags |= IR_USE_FRAME_POINTER;
 			}
-			ctx->flags2 |= IR_HAS_CALLS | IR_16B_FRAME_ALIGNMENT;
+			ctx->flags2 |= IR_HAS_CALLS;
 			return IR_CALL;
 		case IR_VAR:
 			return IR_SKIPPED | IR_VAR;
@@ -941,7 +941,7 @@ binop_fp:
 					}
 				}
 				ctx->flags |= IR_USE_FRAME_POINTER;
-				ctx->flags2 |= IR_HAS_ALLOCA | IR_16B_FRAME_ALIGNMENT;
+				ctx->flags2 |= IR_HAS_ALLOCA;
 			}
 			return IR_ALLOCA;
 		case IR_LOAD:
@@ -5788,12 +5788,12 @@ void ir_fix_stack_frame(ir_ctx *ctx)
 	ctx->stack_frame_alignment = 0;
 	ctx->call_stack_size = 0;
 
-	if ((ctx->flags2 & IR_16B_FRAME_ALIGNMENT) && !(ctx->flags & IR_FUNCTION)) {
+	if (!(ctx->flags & IR_FUNCTION)) {
 		while (IR_ALIGNED_SIZE(ctx->stack_frame_size, 16) != ctx->stack_frame_size) {
 			ctx->stack_frame_size += sizeof(void*);
 			ctx->stack_frame_alignment += sizeof(void*);
 		}
-	} else if (ctx->flags2 & IR_16B_FRAME_ALIGNMENT) {
+	} else {
 		/* Stack must be 16 byte aligned */
 		if (!(ctx->flags & IR_FUNCTION)) {
 			while (IR_ALIGNED_SIZE(ctx->stack_frame_size, 16) != ctx->stack_frame_size) {

diff --git a/tests/bugs/gh-00100.irt b/tests/bugs/gh-00100.irt
@@ -0,0 +1,27 @@
+--TEST--
+GH-100: incorrect stack alignment with VAR on aarch64
+--TARGET--
+aarch64
+--ARGS--
+-O0 -S --run
+--CODE--
+{
+        int32_t c_1 = 42;
+        l_1 = START(l_4);
+        int32_t p = PARAM(l_1, "p", 1);
+        int32_t v = VAR(l_1, "v");
+        l_2 = VSTORE(l_1, v, c_1);
+        int32_t d_3, l_3 = VLOAD(l_2, v);
+        l_4 = RETURN(l_3, d_3);
+}
+--EXPECT--
+main:
+	sub sp, sp, #0x10
+	movz w0, #0x2a
+	str w0, [sp]
+	ldr w0, [sp]
+	add sp, sp, #0x10
+	ret
+
+
+exit code = 42
diff --git a/tests/debug.aarch64/regset-test.irt b/tests/debug.aarch64/regset-test.irt
@@ -149,7 +149,7 @@ R12 (d_35) [%d0]: [35.2-36.1), DEF(35.2)!, USE(36.1/1)!
 [%d1] : [1.0-3.3)
 }
 test:
-	sub sp, sp, #0x38
+	sub sp, sp, #0x40
 	str d0, [sp]
 	ldr d0, .L4
 	fsub d0, d1, d0
@@ -192,10 +192,10 @@ test:
 	cmp w0, #0x3e8
 	b.le .L1
 	mov w0, wzr
-	add sp, sp, #0x38
+	add sp, sp, #0x40
 	ret
 .L3:
-	add sp, sp, #0x38
+	add sp, sp, #0x40
 	ret
 .rodata
 	.db 0x1f, 0x20, 0x03, 0xd5

diff --git a/tests/debug.aarch64/test_var-O0.irt b/tests/debug.aarch64/test_var-O0.irt
@@ -75,7 +75,7 @@ aarch64
 }
 --EXPECT--
 test:
-	sub sp, sp, #0x68
+	sub sp, sp, #0x70
 	str d0, [sp]
 	str d1, [sp, #8]
 	ldr d2, [sp, #8]
@@ -128,14 +128,14 @@ test:
 	fcmp d1, d0
 	b.le .L2
 	ldr w0, [sp, #0x30]
-	add sp, sp, #0x68
+	add sp, sp, #0x70
 	ret
 .L2:
 	ldr w0, [sp, #0x30]
 	cmp w0, #0x3e8
 	b.le .L1
 	mov w0, wzr
-	add sp, sp, #0x68
+	add sp, sp, #0x70
 	ret
 .rodata
 .L3: