Merge branch 'bugfix/potential_wifi_not_work_issue' into 'master'

fix: Fixed a potential issue that wifi may not work (for ESP32-C6 on ESP-IDF v5.1)

See merge request application/esp-at!1465

module_config/module_esp32c6_default/patch/bbpll_calibration.patch

@@ -0,0 +1,101 @@
+diff --git a/components/esp_hw_support/include/esp_private/rtc_clk.h b/components/esp_hw_support/include/esp_private/rtc_clk.h
+index 7edf69be06..c770e94a46 100644
+--- a/components/esp_hw_support/include/esp_private/rtc_clk.h
++++ b/components/esp_hw_support/include/esp_private/rtc_clk.h
+@@ -44,6 +44,11 @@ void rtc_clk_bbpll_add_consumer(void);
+  */
+ void rtc_clk_bbpll_remove_consumer(void);
+
++/**
++ * @brief Workaround for C2, S3, C6, H2. Trigger the calibration of PLL. Should be called when the bootloader doesn't provide a good enough PLL accuracy.
++*/
++void rtc_clk_recalib_bbpll(void);
++
+ #ifdef __cplusplus
+ }
+ #endif
+diff --git a/components/esp_hw_support/port/esp32c6/rtc_clk.c b/components/esp_hw_support/port/esp32c6/rtc_clk.c
+index ed6eb4126f..121907fe85 100644
+--- a/components/esp_hw_support/port/esp32c6/rtc_clk.c
++++ b/components/esp_hw_support/port/esp32c6/rtc_clk.c
+@@ -167,6 +167,7 @@ static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
+     clk_ll_bbpll_set_config(pll_freq, xtal_freq);
+     /* WAIT CALIBRATION DONE */
+     while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
++    esp_rom_delay_us(10);
+     /* BBPLL CALIBRATION STOP */
+     regi2c_ctrl_ll_bbpll_calibration_stop();
+     rtc_clk_enable_i2c_ana_master_clock(false);
+@@ -414,6 +415,22 @@ bool rtc_dig_8m_enabled(void)
+     return clk_ll_rc_fast_digi_is_enabled();
+ }
+
++// Workaround for bootloader not calibration well issue.
++// Placed in IRAM because disabling BBPLL may influence the cache
++void rtc_clk_recalib_bbpll(void)
++{
++    rtc_cpu_freq_config_t old_config;
++    rtc_clk_cpu_freq_get_config(&old_config);
++
++    rtc_clk_cpu_freq_set_xtal();
++
++    rtc_clk_bbpll_disable();
++    rtc_clk_bbpll_enable();
++    rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), 480);
++
++    rtc_clk_cpu_freq_set_config(&old_config);
++}
++
+ /* Name used in libphy.a:phy_chip_v7.o
+  * TODO: update the library to use rtc_clk_xtal_freq_get
+  */
+diff --git a/components/esp_system/Kconfig b/components/esp_system/Kconfig
+index 3006f40b60..f3ab7b0c80 100644
+--- a/components/esp_system/Kconfig
++++ b/components/esp_system/Kconfig
+@@ -561,6 +561,15 @@ menu "ESP System Settings"
+             (2). For special workflow, the chip needs do more things instead of restarting directly. This part
+                  needs to be done in callback function of interrupt.
+
++    config ESP_SYSTEM_BBPLL_RECALIB
++        bool "Re-calibration BBPLL at startup"
++        depends on IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32H2
++        default y
++        help
++            This configuration helps to address an BBPLL inaccurate issue when boot from certain bootloader version,
++            which may increase about the boot-up time by about 200 us. Disable this when your bootloader is built with
++            ESP-IDF version v5.2 and above.
++
+ endmenu  # ESP System Settings
+
+ menu "IPC (Inter-Processor Call)"
+diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c
+index 97a3f767f5..c894ac15ca 100644
+--- a/components/esp_system/port/cpu_start.c
++++ b/components/esp_system/port/cpu_start.c
+@@ -63,6 +63,10 @@
+ #include "esp32c2/rom/secure_boot.h"
+ #endif
+
++#if CONFIG_ESP_SYSTEM_BBPLL_RECALIB
++#include "esp_private/rtc_clk.h"
++#endif
++
+ #include "esp_private/esp_mmu_map_private.h"
+ #if CONFIG_SPIRAM
+ #include "esp_psram.h"
+@@ -454,7 +458,14 @@ void IRAM_ATTR call_start_cpu0(void)
+      * In this stage, we re-configure the Flash (and MSPI) to required configuration
+      */
+     spi_flash_init_chip_state();
++
++    // In earlier version of ESP-IDF, the PLL provided by bootloader is not stable enough.
++    // Do calibration again here so that we can use better clock for the timing tuning.
++#if CONFIG_ESP_SYSTEM_BBPLL_RECALIB
++    rtc_clk_recalib_bbpll();
++#endif
+ #if SOC_MEMSPI_SRC_FREQ_120M
++    // This function needs to be called when PLL is enabled
+     mspi_timing_flash_tuning();
+ #endif
+

module_config/module_esp32c6_default/patch/patch_list.ini

@@ -11,3 +11,7 @@
 [dhcps_poll.patch]
     path = esp-idf
     note = "Fixed an issue that dhcps cannot restore to the default dhcps poll"
+
+[bbpll_calibration.patch]
+    path = esp-idf
+    note = "Fixed a potential issue that wifi may not work (for ESP32-C6 on ESP-IDF v5.1)"