Export project by default

fastmachinelearning · Mar 6, 2018 · feca3e8 · feca3e8
1 parent 0295719
commit feca3e8
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/hls-template/build_prj.tcl b/hls-template/build_prj.tcl
@@ -13,5 +13,5 @@ create_clock -period 5 -name default
 csim_design
 csynth_design
 cosim_design -trace_level all
-#export_design -format ip_catalog
+export_design -format ip_catalog
 exit