use clock product in cggtts solver too

Signed-off-by: Guillaume W. Bres <[email protected]>
georust · Mar 4, 2024 · 6d74dab · 6d74dab
1 parent 23730e9
commit 6d74dab
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Showing 2 changed files with 43 additions and 4 deletions.
diff --git a/rinex-cli/src/positioning/cggtts/mod.rs b/rinex-cli/src/positioning/cggtts/mod.rs
@@ -84,6 +84,20 @@ where
     let nav_data = ctx.data.nav_data().unwrap();
     let meteo_data = ctx.data.meteo_data();
 
+    let clk_data = ctx.data.clk_data();
+    let has_clk_data = clk_data.is_some();
+
+    let sp3_data = ctx.data.sp3_data();
+
+    let sp3_has_clock = if has_clk_data {
+        false // always prefer CLK product
+    } else {
+        match sp3_data {
+            Some(sp3) => sp3.sv_clock().count() > 0,
+            None => false,
+        }
+    };
+
     let dominant_sampling_period = obs_data
         .dominant_sample_rate()
         .expect("RNX2CGGTTS requires steady GNSS observations");
@@ -115,8 +129,34 @@ where
                 continue; // can't proceed further
             }
 
+            // determine TOE
             let (toe, sv_eph) = sv_eph.unwrap();
-            let clock_state = sv_eph.sv_clock();
+            /*
+             * Clock state
+             *  1. Prefer CLK product
+             *  2. Prefer SP3 product
+             *  3. Radio last option
+             */
+            let clock_state = if has_clk_data {
+                let clk = clk_data.unwrap();
+                if let Some((_, profile)) = clk.precise_sv_clock_interpolate(*t, *sv) {
+                    (
+                        profile.bias,
+                        profile.drift.unwrap_or(0.0),
+                        profile.drift_change.unwrap_or(0.0),
+                    )
+                } else {
+                    /*
+                     * do not interpolate other products: abort
+                     */
+                    continue;
+                }
+            } else if sp3_has_clock {
+                panic!("sp3 (clock) interpolation not ready yet: prefer broadcast or clk product");
+            } else {
+                sv_eph.sv_clock()
+            };
+            // determine clock correction
             let clock_corr = Ephemeris::sv_clock_corr(*sv, clock_state, *t, toe);
             let clock_state = Vector3::new(clock_state.0, clock_state.1, clock_state.2);
 

diff --git a/rinex-cli/src/positioning/ppp/mod.rs b/rinex-cli/src/positioning/ppp/mod.rs
@@ -36,7 +36,7 @@ where
     let sp3_data = ctx.data.sp3_data();
 
     let sp3_has_clock = if has_clk_data {
-        false // always prefer clk data
+        false // always prefer CLK product
     } else {
         match sp3_data {
             Some(sp3) => sp3.sv_clock().count() > 0,
@@ -77,7 +77,6 @@ where
              */
             let clock_state = if has_clk_data {
                 let clk = clk_data.unwrap();
-
                 if let Some((_, profile)) = clk.precise_sv_clock_interpolate(*t, *sv) {
                     (
                         profile.bias,
@@ -91,7 +90,7 @@ where
                     continue;
                 }
             } else if sp3_has_clock {
-                unimplemented!("unhandled case");
+                panic!("sp3 (clock) interpolation not ready yet: prefer broadcast or clk product");
             } else {
                 sv_eph.sv_clock() // BRDC case
             };