NYU ProcDesign Core

The NYU ProcDesign Core will be a RISCV-32I compatible core with a 5-stage pipeline.

The repo contains the modules and test for components that make up the core design.

The progress tracker for individual components can be found here.

You can find our getting started document here.

Core Components

The core modules include:

• Arithmatic Logic Unit (ALU)
• General Registers
• Program Counter

Branching Logic

The branch logic modules include:

• Branch Evaluator
• Branch Predictor
• Branch Address Calculator
• Branch Manager

Pipeline

The pipeline will have 5 stages:

• Instruction Fetch (IF)
• Instruction Decode (ID)
• Execution (EX)
• Memory Access (MEM)
• Write Back (WB)

The pipeline will require 4 latch modules:

• IF/ID Latch
• ID/EX Latch
• EX/MEM Latch
• MEM/WB Latch

General Control and Hazards

Control Modules:

• Processor State Module
• Pipeline Reset Module

Caches

Cache Modules:

• Instruction Cache Manager
• L1 Instruction Cache
• Data Cache Manager
• L1 Data Cache

Current Draft of CPU Diagram

Further Reading

Development and Testing Guidelines

Offical RISCV Unprivileged Instruction Set Documentation