Add support for a DMA based TMC UART

This provides a DMA based implementation for a UART interface to TMC22XX
drivers. Output bits are transmitted using a series of chained DMA
descriptors which set/clr the GPIO bits as required. The response is
read by capturing a series of samples from the GPIO pin and then
processing them to extract the UART bits. This implmenetation has a
considerably lower interrupt overhead than the alternate timer based
implementation. However it does require approximately 360 bytes of
memory for the DMA I/O buffer. The DMA transfer makes use of TIMER1
which currently means that this version can not be used at the same time
as the ADC smoothing feature (which also makes use of TIMER1).

NOTE: During the testing of this code it was noted that the DMA writes
sometimes resulted in corrupt pin output. It was determined that this
was caused by the DMA write being interleaved with other write
operations on the same port. It would seem that even though the other
writes were being made using the bit banding feature they still
resulted in a read/modify/write sequence which was open to corruption by
both the DMA write and by other write operations performed at interrupt
time. Using the GPIO SET/CLR registers to perform the normal write
operations seems to resolve the issue.