Implement Host Driver support for synopsys dwc2 #2870
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check request queue available before making usb attempt. Though there is no handling when queue is full. device_info example work well
…asier to manage. Fix channel disable/deallocated.
…action per transfer
…orer example read work, but write10 still wip
… for OUT. msc explorer seems to work well.
… better out dma handle
… port speed. Enable low power UTMI+ phy mode for ls/fs device.
fix duplicated device attach for some devices which cause "USBH Defer Attach until current enumeration complete" include dev0 for tuh_edpt_abort_xfer()
…slave it enumerate device but has issue with msc bulk in
…s increased but data transfer over USB is not correct.
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| // void dwc2_core_handle_common_irq(uint8_t rhport, bool in_isr) { | ||
| // (void) in_isr; | ||
| // dwc2_regs_t * const dwc2 = DWC2_REG(rhport); | ||
| // const uint32_t int_mask = dwc2->gintmsk; | ||
| // const uint32_t int_status = dwc2->gintsts & int_mask; | ||
| // | ||
| // // Device disconnect | ||
| // if (int_status & GINTSTS_DISCINT) { | ||
| // dwc2->gintsts = GINTSTS_DISCINT; | ||
| // } | ||
| // | ||
| // } |
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| uint32_t speed : 2; | ||
| uint32_t next_pid : 2; | ||
| uint32_t do_ping : 1; | ||
| // uint32_t : 9; |
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| // if (channel->hcsplt_bm.split_en) { | ||
| // if (edpt->hcchar_bm.ep_num == 1) { | ||
| // TU_LOG1("Frame %u, ch %u: ep %u, hcint 0x%04lX ", dwc2->hfnum_bm.num, ch_id, channel->hcchar_bm.ep_num, hcint); | ||
| // print_hcint(hcint); | ||
| // } |
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| bool is_done = false; | ||
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| // TU_LOG1("in hcint = %02lX\r\n", hcint); |
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| bool is_done = false; | ||
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| // TU_LOG1("out hcint = %02lX\r\n", hcint); |
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| // Port enable | ||
| port0_enable(dwc2); | ||
| } else { | ||
| // TU_ASSERT(false, ); |
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| const uint32_t gintmsk = dwc2->gintmsk; | ||
| const uint32_t gintsts = dwc2->gintsts & gintmsk; | ||
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| // TU_LOG1_HEX(gintsts); |
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Hint: cache synchronization is absent. |
Thank you for the hint, I am a bit exausted with hcd dwc2 feature for now and not used with debugging esp32p4 (got openocd run, but one it hit breakpoint any futher steps cause it to panic), also printf in isr may also cause panic. I will call it a day for now, since it still function well with slave mode. I will come back to this later on. |
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of note, cache coherency is also a problem with my own dwc2 hcd on the rpi (need to test this PR out and see how it behaves) in my case, i have cache management hooks in the HCD, but one of my buffers was stack allocated, and some activity on the stack caused it to get pulled back into the cache before a control-in could complete |
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@cleverca22 for ARM cores please use MPU to mark the buffer area as non cacheable instead of doing cache clean/invalidate, similar to what #2865 does. PS: MCHP has nice write-up on cache https://ww1.microchip.com/downloads/en/DeviceDoc/Managing-Cache-Coherency-on-Cortex-M7-Based-MCUs-DS90003195A.pdf |
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@HiFiPhile in my case, i happen to be on cortex-a, so thats handled in the MMU the problem is more, that tinyusb and other applications, are putting the DMA buffers in places like the stack or so you need to get everything using tinyusb to allocate buffers from a fixed pool edit: |
Doesn't using |
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@HiFiPhile actually, we can also support dcache clean/invalidate as well, application only need to have the CFG_TUH_MEM_ALIGN to 64 for cache line. It can cost ram, but for some port such as broadcom bcm2711 (pi4) it does not matter. So yeah, I don't rule out option for dcache support. Though I haven't added dcahe for dwc2 yet (I think we did it for chipidea), will do later. |
The buffer size also has to be multiple of cache line size, otherwise cached data will be crashed doing cache clean. There is an example in my linked document. |
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yeah, if it is application buffer, it should also be cachline aligned. For us, we need to make sure any buffer for communicated must be CFG_TUH_MEM_ALIGN. PS: I test this dcache later on. really exausted with hcd dwc2 for now |
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something ive been thinking, is that a cache discard (no clean allowed) would also be of use basically, you have buffers in 2 pools, cpu->device, and device->cpu any time you write to a cpu->device buffer, you can do a cache clean, to flush the changes to dram, because the region is only ever written by the cpu, there is never dirty data at risk of being caught up, so you dont have to align by cache line size any time the device is done doing dma and your informing tinyusb, you discard the cache for the entire area but this idea now complicates things, because you need 2 versions of |
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@hathach @HiFiPhile |
For CDC there is a script #920 |
Describe the PR
Add host driver for synopsys dwc2 (esp32-s2/s3/p4, stm32, etc..)
tusb_time_millis_api()andtusb_time_delay_ms_api()(default to blocking with millis_api()` which is reuired for no rtos when using with some port/configuration e.g hcd dwc2.USBH Defer Attach until current enumeration completemessageKnown issue: For esp32-p4, buffer DMA doees not work (use slave for now). Not entirely sure why, chip support desc dma, but we haven't enabled it yet. I notice hcddma address is increased corretly when sending setup, but data is random (not correct). fix or implement ddma later