Temp7

hdl · Nov 1, 2023 · 0a303b1 · 0a303b1
1 parent 5e39c48
commit 0a303b1
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diff --git a/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27_rvt_4x-cells.bzl b/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27_rvt_4x-cells.bzl
@@ -12,7 +12,9 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
-# ASAP7 "rev 27" 7.5 track standard cell library using regular VT transistors
+##########################################################################
+# Special 4x scaled version of the ASAP7 "rev 27" 7.5 track standard cell
+# library using regular VT transistors.
 ##########################################################################
 
 # Layouts for GDS generation
@@ -23,52 +25,52 @@
 # timing analysis (STA).
 # ------------------------------------------------------------------------
 alias(
-    name = "asap7-sc7p5t_rev27_rvt_4x-cells-libgz",
-    actual = ":asap7-sc7p5t_rev27_rvt-cells-libgz",
+    name = "asap7-cells-sc7p5t_rev27_rvt_4x-libgz",
+    actual = ":asap7-cells-sc7p5t_rev27_rvt-libgz",
 )
 
 # Verilog models for digital simulation and logical equivalence
 # ------------------------------------------------------------------------
 alias(
-    name = "asap7-sc7p5t_rev27_rvt_4x-cells-v",
-    actual = ":asap7-sc7p5t_rev27_rvt-cells-v",
+    name = "asap7-cells-sc7p5t_rev27_rvt_4x-v",
+    actual = ":asap7-cells-sc7p5t_rev27_rvt-v",
 )
 
 # CDL models for LVS checking
 # ------------------------------------------------------------------------
 alias(
-    name = "asap7-sc7p5t_rev27_rvt_4x-cells-lvs",
-    actual = ":asap7-sc7p5t_rev27_rvt-cells-lvs",
+    name = "asap7-cells-sc7p5t_rev27_rvt_4x-lvs",
+    actual = ":asap7-cells-sc7p5t_rev27_rvt-lvs",
 )
 
 # CDL models for Spice simulation
 # ------------------------------------------------------------------------
-filegroup(
-    name = "asap7-sc7p5t_rev27_rvt_4x-cells-spice",
-    actual = ":asap7-sc7p5t_rev27_rvt-cells-spice",
+alias(
+    name = "asap7-cells-sc7p5t_rev27_rvt_4x-spice",
+    actual = ":asap7-cells-sc7p5t_rev27_rvt-spice",
 )
 
 # Place and route
 # ------------------------------------------------------------------------
 filegroup(
-    name = "asap7-sc7p5t_rev27_rvt_4x-cells-lef",
+    name = "asap7-cells-sc7p5t_rev27_rvt_4x-lef",
     srcs = ["asap7sc7p5t_27/LEF/scaled/asap7sc7p5t_27_R_4x_220121a.lef"],
 )
 
 # Library configuration
 # ------------------------------------------------------------------------
 asap7_cell_library(
-    name = "asap7-sc7p5t_rev27_rvt",
+    name = "asap7-sc7p5t_rev27_rvt_4x",
     srcs = [
-	":asap7-sc7p5t_rev27_rvt_4x-cells-libgz",
-#	":asap7-sc7p5t_rev27-srams-libgz",
+	":asap7-cells-sc7p5t_rev27_rvt_4x-libgz",
+#	":asap7-srams-sc7p5t_rev27_4x-libgz",
     ],
-    cell_lef = ":asap7-sc7p5t_rev27_rvt_4x-cells-lef",
-#    platform_gds = ":asap7-sc7p5t_rev27_rvt_4x-cells-gds",
+    cell_lef = ":asap7-cells-sc7p5t_rev27_rvt_4x-lef",
+#    platform_gds = ":asap7-cells-sc7p5t_rev27_rvt_4x-gds",
     default_corner_delay_model = "ccs",
     default_corner_swing = "SS",
     openroad_configuration = ":open_road-asap7-sc7p5t_rev27_rvt_4x",
-    tech_lef = ":asap7-sc7p5t_rev27_4x-tech-lef",
+    tech_lef = ":asap7-misc-sc7p5t_rev27_4x-lef",
     visibility = [
         "//visibility:public",
     ]
@@ -122,3 +124,6 @@ open_road_pdk_configuration(
     wire_rc_clock_metal_layer = "M5",
     wire_rc_signal_metal_layer = "M2",
 )
+
+##########################################################################
+##########################################################################
diff --git a/dependency_support/org_theopenroadproject_asap7/asap7.bzl b/dependency_support/org_theopenroadproject_asap7/asap7.bzl
@@ -4,115 +4,118 @@ load("@rules_hdl//pdk:build_defs.bzl", "CornerInfo", "StandardCellInfo")
 load("@rules_hdl//pdk:open_road_configuration.bzl", "OpenRoadPdkInfo")
 
 
-def _asap7_srams_files_impl(ctx):
+def asap7_srams_files(name=None, rev=None, tracks=None):
+    if rev not in ["26", "27", "28"]:
+        fail("Invalid rev {}".format(repr(rev)))
+    if tracks not in ["7p5t", "6t"]:
+        fail("Invalid rev {}".format(repr(tracks)))
+
     args = {
-        'rev': str(ctx.attr.rev),
-        'tracks': str(ctx.attr.tracks),
+        'rev': str(rev),
+        'tracks': str(tracks),
     }
 
     # Layouts for GDS generation
     # ------------------------------------------------------------------------
-    ctx.actions.filegroup(
+    native.filegroup(
         name = "asap7-srams-sc{tracks}_rev{rev}-gds".format(**args),
-        srcs = ctx.glob(["asap7sc{tracks}_{rev}/GDS/asap7sc{tracks}_{rev}*_SRAM_*.gds".format(**args)]),
+        srcs = native.glob(["asap7sc{tracks}_{rev}/GDS/asap7sc{tracks}_{rev}*_SRAM_*.gds".format(**args)]),
     )
 
     # Timing information (in compressed Liberty format) for synthesis and static
     # timing analysis (STA).
     # ------------------------------------------------------------------------
-    ctx.actions.filegroup(
+    native.filegroup(
         name = "asap7-srams-sc{tracks}_rev{rev}-libgz".format(**args),
-        srcs = ctx.glob(["asap7sc{tracks}_{rev}/LIB/CCS/*SRAM*.lib.gz".format(**args)]),
+        srcs = native.glob(["asap7sc{tracks}_{rev}/LIB/CCS/*SRAM*.lib.gz".format(**args)]),
     )
 
     # Verilog models for digital simulation and logical equivalence
     # ------------------------------------------------------------------------
-    ctx.actions.filegroup(
+    native.filegroup(
         name = "asap7-srams-sc{tracks}_rev{rev}-v".format(**args),
-        srcs = ctx.glob(["asap7sc{tracks}_{rev}/Verilog/asap7sc{tracks}_*_SRAM_*.v".format(**args)]),
+        srcs = native.glob(["asap7sc{tracks}_{rev}/Verilog/asap7sc{tracks}_*_SRAM_*.v".format(**args)]),
     )
 
     # CDL models for LVS checking
     # ------------------------------------------------------------------------
-    ctx.actions.filegroup(
+    native.filegroup(
         name = "asap7-srams-sc{tracks}_rev{rev}-lvs".format(**args),
         srcs = ["asap7sc{tracks}_{rev}/CDL/LVS/asap7sc{tracks}_{rev}_*SRAM*.cdl".format(**args)],
     )
 
     # CDL models for Spice simulation
     # ------------------------------------------------------------------------
-    ctx.actions.filegroup(
+    native.filegroup(
         name = "asap7-srams-sc{tracks}_rev{rev}-spice".format(**args),
         srcs = ["asap7sc{tracks}_{rev}/CDL/xAct3D_extracted/asap7sc{tracks}_{rev}_*SRAM*.sp".format(**args)],
     )
 
     # Place and route
     # ------------------------------------------------------------------------
-    ctx.actions.filegroup(
+    native.filegroup(
         name = "asap7-srams-sc{tracks}_rev{rev}-lef".format(**args),
         srcs = ["asap7sc{tracks}_{rev}/LEF/asap7sc{tracks}_{rev}*_SRAM_*.lef".format(**args)],
     )
 
 
-asap7_srams_files = rule(
-    implementation = _asap7_srams_files_impl,
-    attrs = {
-        "rev": attr.string(mandatory = True),
-        "tracks": attr.string(mandatory = True, values = ["7p5t", "6t"]),
-    },
-)
-
+def asap7_cells_files(name=None, rev=None, tracks=None, vt=None):
+    if rev not in ["26", "27", "28"]:
+        fail("Invalid rev {}".format(repr(rev)))
+    if tracks not in ["7p5t", "6t"]:
+        fail("Invalid tracks {}".format(repr(tracks)))
+    if vt not in ["lvt", "rvt", "slvt"]:
+        fail("Invalid vt {}".format(repr(vt)))
 
-def _asap7_cells_files_impl(ctx):
     args = {
-        'rev': str(ctx.attr.rev),
-        'tracks': str(ctx.attr.tracks),
-        'vt_long': str(ctx.attr.vt),
-        'vt_upper': str(ctx.attr.vt).upper(),
-        'vt_short': {'rvt': 'R', 'lvt': 'L', 'slvt': 'SL'}[str(ctx.attr.vt)],
+        'rev': rev,
+        'tracks': tracks,
+        'vt_long': vt,
+        'vt_upper': vt.upper(),
+        'vt_short': {'rvt': 'R', 'lvt': 'L', 'slvt': 'SL'}[vt],
     }
 
     # Layouts for GDS generation
     # ------------------------------------------------------------------------
-    ctx.actions.filegroup(
+    native.filegroup(
         name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-gds".format(**args),
-        srcs = ctx.glob(["asap7sc{tracks}_{rev}/GDS/asap7sc{tracks}_{rev}_{vt_short}_220121a.gds".format(**args)]),
+        srcs = native.glob(["asap7sc{tracks}_{rev}/GDS/asap7sc{tracks}_{rev}_{vt_short}*.gds".format(**args)]),
     )
 
     # Timing information (in compressed Liberty format) for synthesis and static
     # timing analysis (STA).
     # ------------------------------------------------------------------------
-    ctx.actions.filegroup(
+    native.filegroup(
         name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-libgz".format(**args),
-        srcs = ctx.glob(["asap7sc{tracks}_{rev}/LIB/CCS/*{vt_upper}*.lib.gz".format(**args)]),
+        srcs = native.glob(["asap7sc{tracks}_{rev}/LIB/CCS/*_{vt_upper}_*.lib.gz".format(**args)]),
     )
 
     # Verilog models for digital simulation and logical equivalence
     # ------------------------------------------------------------------------
-    ctx.actions.filegroup(
+    native.filegroup(
         name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-v".format(**args),
-        srcs = ctx.glob(["asap7sc{tracks}_{rev}/Verilog/asap7sc{tracks}_*_{vt_upper}_*.v".format(**args)]),
+        srcs = native.glob(["asap7sc{tracks}_{rev}/Verilog/asap7sc{tracks}_*_{vt_upper}_*.v".format(**args)]),
     )
 
     # CDL models for LVS checking
     # ------------------------------------------------------------------------
-    ctx.actions.filegroup(
+    native.filegroup(
         name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lvs".format(**args),
-        srcs = ["asap7sc{tracks}_{rev}/CDL/LVS/asap7sc{tracks}_{rev}_{vt_short}.cdl".format(**args)],
+        srcs = native.glob(["asap7sc{tracks}_{rev}/CDL/LVS/asap7sc{tracks}_{rev}_{vt_short}.cdl".format(**args)]),
     )
 
     # CDL models for Spice simulation
     # ------------------------------------------------------------------------
-    ctx.actions.filegroup(
+    native.filegroup(
         name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-spice".format(**args),
-        srcs = ["asap7sc{tracks}_{rev}/CDL/xAct3D_extracted/asap7sc{tracks}_{rev}_{vt_short}.sp".format(**args)],
+        srcs = native.glob(["asap7sc{tracks}_{rev}/CDL/xAct3D_extracted/asap7sc{tracks}_{rev}_{vt_short}.sp".format(**args)]),
     )
 
     # Place and route
     # ------------------------------------------------------------------------
-    ctx.actions.filegroup(
+    native.filegroup(
         name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lef".format(**args),
-        srcs = ["asap7sc{tracks}_{rev}/LEF/asap7sc{tracks}_{rev}_{vt_short}_1x_220121a.lef".format(**args)],
+        srcs = native.glob(["asap7sc{tracks}_{rev}/LEF/asap7sc{tracks}_{rev}_{vt_short}_1x*.lef".format(**args)]),
     )
 
     # Library configuration
@@ -128,22 +131,13 @@ def _asap7_cells_files_impl(ctx):
         default_corner_delay_model = "ccs",
         default_corner_swing = "SS",
         openroad_configuration = ":open_road-asap7-sc{tracks}_rev{rev}_{vt_long}".format(**args),
-        tech_lef = ":asap7-tech-sc{tracks}_rev{rev}-lef".format(**args),
+        tech_lef = ":asap7-misc-sc{tracks}_rev{rev}-lef".format(**args),
         visibility = [
             "//visibility:public",
         ]
     )
 
 
-asap7_cells_files = rule(
-    implementation = _asap7_cells_files_impl,
-    attrs = {
-        "rev": attr.string(mandatory = True),
-        "tracks": attr.string(mandatory = True, values = ["7p5t", "6t"]),
-        "vt":  attr.string(mandatory = True, values = ["RVT", "LVT", "SLVT"]),
-    },
-)
-
 def _asap7_cell_library_impl(ctx):
     liberty_files = [file for file in ctx.files.srcs if file.extension == "gz"]
     liberty_files = [file for file in liberty_files if "_{}_".format(ctx.attr.default_corner_delay_model) in file.basename]
@@ -211,7 +205,7 @@ asap7_cell_library = rule(
         #TODO(b/212480812): Support multiple VTs in a single design.
         "openroad_configuration": attr.label(providers = [OpenRoadPdkInfo]),
         "cell_lef": attr.label(allow_single_file = True, mandatory = True, doc = "The lef file for the standard cells"),
-        "platform_gds": attr.label(allow_single_file = True, mandatory = True, doc = "Platform GDS files"),
+        "platform_gds": attr.label(allow_single_file = True, mandatory = False, doc = "Platform GDS files"),
         "_combine_liberty": attr.label(
             default = Label("@rules_hdl//pdk/liberty:combine_liberty"),
             executable = True,

diff --git a/dependency_support/org_theopenroadproject_asap7/bundled.BUILD.bazel b/dependency_support/org_theopenroadproject_asap7/bundled.BUILD.bazel
@@ -284,7 +284,9 @@ open_road_pdk_configuration(
 )
 
 # From asap7-sc7p5t_rev27_rvt_4x-cells.bzl
-# ASAP7 "rev 27" 7.5 track standard cell library using regular VT transistors
+##########################################################################
+# Special 4x scaled version of the ASAP7 "rev 27" 7.5 track standard cell
+# library using regular VT transistors.
 ##########################################################################
 
 # Layouts for GDS generation
@@ -295,52 +297,52 @@ open_road_pdk_configuration(
 # timing analysis (STA).
 # ------------------------------------------------------------------------
 alias(
-    name = "asap7-sc7p5t_rev27_rvt_4x-cells-libgz",
-    actual = ":asap7-sc7p5t_rev27_rvt-cells-libgz",
+    name = "asap7-cells-sc7p5t_rev27_rvt_4x-libgz",
+    actual = ":asap7-cells-sc7p5t_rev27_rvt-libgz",
 )
 
 # Verilog models for digital simulation and logical equivalence
 # ------------------------------------------------------------------------
 alias(
-    name = "asap7-sc7p5t_rev27_rvt_4x-cells-v",
-    actual = ":asap7-sc7p5t_rev27_rvt-cells-v",
+    name = "asap7-cells-sc7p5t_rev27_rvt_4x-v",
+    actual = ":asap7-cells-sc7p5t_rev27_rvt-v",
 )
 
 # CDL models for LVS checking
 # ------------------------------------------------------------------------
 alias(
-    name = "asap7-sc7p5t_rev27_rvt_4x-cells-lvs",
-    actual = ":asap7-sc7p5t_rev27_rvt-cells-lvs",
+    name = "asap7-cells-sc7p5t_rev27_rvt_4x-lvs",
+    actual = ":asap7-cells-sc7p5t_rev27_rvt-lvs",
 )
 
 # CDL models for Spice simulation
 # ------------------------------------------------------------------------
-filegroup(
-    name = "asap7-sc7p5t_rev27_rvt_4x-cells-spice",
-    actual = ":asap7-sc7p5t_rev27_rvt-cells-spice",
+alias(
+    name = "asap7-cells-sc7p5t_rev27_rvt_4x-spice",
+    actual = ":asap7-cells-sc7p5t_rev27_rvt-spice",
 )
 
 # Place and route
 # ------------------------------------------------------------------------
 filegroup(
-    name = "asap7-sc7p5t_rev27_rvt_4x-cells-lef",
+    name = "asap7-cells-sc7p5t_rev27_rvt_4x-lef",
     srcs = ["asap7sc7p5t_27/LEF/scaled/asap7sc7p5t_27_R_4x_220121a.lef"],
 )
 
 # Library configuration
 # ------------------------------------------------------------------------
 asap7_cell_library(
-    name = "asap7-sc7p5t_rev27_rvt",
+    name = "asap7-sc7p5t_rev27_rvt_4x",
     srcs = [
-	":asap7-sc7p5t_rev27_rvt_4x-cells-libgz",
-#	":asap7-sc7p5t_rev27-srams-libgz",
+	":asap7-cells-sc7p5t_rev27_rvt_4x-libgz",
+#	":asap7-srams-sc7p5t_rev27_4x-libgz",
     ],
-    cell_lef = ":asap7-sc7p5t_rev27_rvt_4x-cells-lef",
-#    platform_gds = ":asap7-sc7p5t_rev27_rvt_4x-cells-gds",
+    cell_lef = ":asap7-cells-sc7p5t_rev27_rvt_4x-lef",
+#    platform_gds = ":asap7-cells-sc7p5t_rev27_rvt_4x-gds",
     default_corner_delay_model = "ccs",
     default_corner_swing = "SS",
     openroad_configuration = ":open_road-asap7-sc7p5t_rev27_rvt_4x",
-    tech_lef = ":asap7-sc7p5t_rev27_4x-tech-lef",
+    tech_lef = ":asap7-cells-sc7p5t_rev27_4x-tech-lef",
     visibility = [
         "//visibility:public",
     ]
@@ -395,6 +397,9 @@ open_road_pdk_configuration(
     wire_rc_signal_metal_layer = "M2",
 )
 
+##########################################################################
+##########################################################################
+
 # From asap7-sc7p5t_rev27_slvt-cells.bzl
 # ASAP7 "rev 27" 7.5 track standard cell library using Super-Low VT transistors
 # ------------------------------------------------------------------------