Final Project README

Run C Simulation

• ecelinux

To run the software on ecelinux, first go to the 6775-Final-Project/fpga/src directory, then run make test

The simulation result will be write into test_output_low.txt with paired bestEnergy and spins.

To check the functionality of dut and host program on software, run make test_host. test_output_host.txt should give exactly the same bestEnergy and spins as test_output_low.txt gives.

cd 6775-Final-Project/fpga/src # main path

source /classes/ece6775/setup-ece6775.sh # setup env

make test # do software simulation for functionality

make test_host # do software simulation with dut/host program

Run C Synthesis

cd 6775-Final-Project/fpga/src # main path

source /classes/ece6775/setup-ece6775.sh # setup env

vivado_hls -f run_base.tcl # C Synthesis

Generating the Bitstream

1. The first step is to generate verilog from HLS

# In ecelinux
cd 6775-Final-Project/fpga/src # main path

source /classes/ece6775/setup-ece6775.sh # setup env

make test # builds and runs the csim

# generate Verilog
vivado_hls -f run_base.tcl

You can examine the directory cordic.prj/solution1/syn/verilog to check that the Verilog files have been generated.

2. The next step is to implement the hardware circuit described by the Verilog on an the FPGA.

source run_bitstream.sh # generate FPGA bitstream

Programming the FPGA

Before you attempt to login, please first check the occupancy of the available boards using the following link: https://www.csl.cornell.edu/courses/ece6775/zedboard.html

zhang-zedboard-xx.ece.cornell.edu

where xx can be 01, 02, ..., 11.

All students have an account on each Zedboard with their NetID as the username and their case-sensitive last name as their initial password.

# In ecelinux,
# Copy the bitstream from ecelinux to Zedboard
scp xillydemo.bit [email protected]:~

# Login to the Zedboard
ssh [email protected]

# In Zedboard
# Mount SD card. Try rebooting if there is a device busy error
mount /mnt/sd

# Copy the bitstream file to the SD card and reboot the Zedboard
cp xillydemo.bit /mnt/sd

sudo reboot # restart Zedboard

The Zedboard will restart. Wait about 30 seconds and login again — the FPGA will be fully programmed after the reboot

Run FPGA Experiment

• Zedboard

To run the FPGA experiment on a Zedboard, first copy 6775-Final-Project files to a Zedboard,

# in ecelinux
zip -r final_project.zip 6775-Final-Project  # zip the file

scp final_project.zip <user>@zhang-zedboard-xx.ece.cornell.edu:~ # copy zip file to zedboard

ssh <user>@zhang-zedboard-xx.ece.cornell.edu # log in to a Zedboard

then go to the directory 6775-Final-Project/fpga/src, finally run make fpga.

Notice, need to rename Makefile_fpga to Makefile so run on Zedboard environment.

# in zedboard
unzip final_project.zip # unzip the archive

cd 6775-Final-Project/fpga/src # main path

mv Makefile_fpga Makefile # for Zedboard Environment

make fpga # builds and runs FPGA experiment

Verification

By comparing the generated txt file for best energy and paired spins, with the printed result in terminal on Zedboard, they should give the same result. This verify that our dut/host program work correctly.