Updating papi_events.csv to support addition of L1I_CACHE and depreca…

…tion of L1I_CACHE_ACCESS in libpfm4.

Testing took place on a Neoverse V2 by comparing output from the commit
prior to the addition of L1I_CACHE and the commit that adds L1I_CACHE.

- Output for papi_avail was identical
- Output for papi_command_line for the events PAPI_L1_ICA, PAPI_L1_ICH,
  PAPI_L1_TCA, and PAPI_L1_TCH was roughly identical.

src/papi_events.csv

@@ -2236,8 +2236,8 @@ PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE
 PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL
 PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD
 PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR
-PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS
-PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE_ACCESS,L1I_CACHE_REFILL
+PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE
+PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE,L1I_CACHE_REFILL
 PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
 PRESET,PAPI_L2_TCA,NOT_DERIVED,L2D_CACHE_ACCESS
 PRESET,PAPI_L2_DCA,DERIVED_ADD,L2D_CACHE_RD,L2D_CACHE_WR
@@ -2271,8 +2271,8 @@ PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE
 PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL
 PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD
 PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR
-PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS
-PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE_ACCESS,L1I_CACHE_REFILL
+PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE
+PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE,L1I_CACHE_REFILL
 PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
 PRESET,PAPI_L2_TCA,NOT_DERIVED,L2D_CACHE_ACCESS
 PRESET,PAPI_L2_DCA,DERIVED_ADD,L2D_CACHE_RD,L2D_CACHE_WR
@@ -2306,8 +2306,8 @@ PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE
 PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL
 PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD
 PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR
-PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS
-PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE_ACCESS,L1I_CACHE_REFILL
+PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE
+PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE,L1I_CACHE_REFILL
 PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
 PRESET,PAPI_L2_TCA,NOT_DERIVED,L2D_CACHE_ACCESS
 PRESET,PAPI_L2_DCA,DERIVED_ADD,L2D_CACHE_RD,L2D_CACHE_WR
@@ -2373,15 +2373,15 @@ PRESET,PAPI_L1_DCH,DERIVED_SUB,L1D_CACHE,L1D_CACHE_REFILL
 PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL
 PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD
 PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR
-PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS
-PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE_ACCESS,L1I_CACHE_REFILL
+PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE
+PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE,L1I_CACHE_REFILL
 PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
 #NOT_IMPLEMENTED,PAPI_L1_ICR,Level 1 instruction cache reads
 #NOT_IMPLEMENTED,PAPI_L1_ICW,Level 1 instruction cache writes
 #NOT_IMPLEMENTED,PAPI_L1_LDM,Level 1 load misses
 #NOT_IMPLEMENTED,PAPI_L1_STM,Level 1 store misses
-PRESET,PAPI_L1_TCA,DERIVED_ADD,L1D_CACHE,L1I_CACHE_ACCESS
-PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|-|,L1D_CACHE,L1D_CACHE_REFILL,L1I_CACHE_ACCESS,L1I_CACHE_REFILL
+PRESET,PAPI_L1_TCA,DERIVED_ADD,L1D_CACHE,L1I_CACHE
+PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|-|,L1D_CACHE,L1D_CACHE_REFILL,L1I_CACHE,L1I_CACHE_REFILL
 PRESET,PAPI_L1_TCM,DERIVED_ADD,L1D_CACHE_REFILL,L1I_CACHE_REFILL
 #NOT_IMPLEMENTED,PAPI_L1_TCR,Level 1 total cache reads
 #NOT_IMPLEMENTED,PAPI_L1_TCW,Level 1 total cache writes