[SYCL] Add LNL and BMG to device config file (#15194)

Follow up to #14188 adding LNL and BMG target info.
intel · Sep 3, 2024 · 7f9e251 · 7f9e251
1 parent 8730002
commit 7f9e251
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diff --git a/llvm/include/llvm/SYCLLowerIR/DeviceConfigFile.td b/llvm/include/llvm/SYCLLowerIR/DeviceConfigFile.td
@@ -176,6 +176,8 @@ class IntelTargetInfo<string Name, list<Aspect> Aspects, list<int> subGroupSizes
 : TargetInfo<Name, IntelBaseAspects # Aspects, subGroupSizesList>;
 // Note: only the "canonical" target names are listed here - see
 // SYCL::gen::resolveGenDevice().
+def : IntelTargetInfo<"intel_gpu_bmg_g21", Fp16Fp64Atomic64, Sg16_32>;
+def : IntelTargetInfo<"intel_gpu_lnl_m", Fp16Fp64Atomic64, Sg16_32>;
 def : IntelTargetInfo<"intel_gpu_arl_h", Fp16Fp64Atomic64, Sg8_16_32>;
 def : IntelTargetInfo<"intel_gpu_mtl_h", Fp16Fp64Atomic64, Sg8_16_32>;
 def : IntelTargetInfo<"intel_gpu_mtl_u", Fp16Fp64Atomic64, Sg8_16_32>;

diff --git a/llvm/test/tools/sycl-post-link/multiple-filtered-outputs.ll b/llvm/test/tools/sycl-post-link/multiple-filtered-outputs.ll
@@ -8,6 +8,8 @@
 ; RUN: -o intel_gpu_pvc,%t-pvc.table \
 ; RUN: -o intel_gpu_tgllp,%t-tgllp.table \
 ; RUN: -o intel_gpu_cfl,%t-cfl.table \
+; RUN: -o intel_gpu_lnl_m,%t-lnl.table \
+; RUN: -o intel_gpu_bmg_g21,%t-bmg.table \
 ; RUN: -o unrecognized_target,%t-unrecognized.table
 
 ; RUN: FileCheck %s -input-file=%t_0.sym -check-prefix=CHECK-DOUBLE
@@ -22,6 +24,8 @@
 ; RUN: FileCheck %s -input-file=%t-pvc.table -check-prefix=CHECK-PVC
 ; RUN: FileCheck %s -input-file=%t-tgllp.table -check-prefix=CHECK-TGLLP
 ; RUN: FileCheck %s -input-file=%t-cfl.table -check-prefix=CHECK-CFL
+; RUN: FileCheck %s -input-file=%t-lnl.table -check-prefix=CHECK-LNL
+; RUN: FileCheck %s -input-file=%t-bmg.table -check-prefix=CHECK-BMG
 
 ; CHECK-DOUBLE: double_kernel
 ; CHECK-FLOAT: float_kernel
@@ -81,6 +85,20 @@
 ; RUN: FileCheck %s -input-file=%t_intel_gpu_cfl_5.prop -check-prefix=CHECK-CFL-PROP
 ; CHECK-CFL-PROP: compile_target=2|oBAAAAAAAAQauRXZs91ZwV3XjZGb
 
+; LNL does not support sg8 (=1) or sg64 (=2)
+; CHECK-LNL:      _intel_gpu_lnl_m_0.prop|{{.*}}_0.sym
+; CHECK-LNL-NEXT: _intel_gpu_lnl_m_3.prop|{{.*}}_3.sym
+; CHECK-LNL-NEXT: _intel_gpu_lnl_m_4.prop|{{.*}}_4.sym
+; CHECK-LNL-NEXT: _intel_gpu_lnl_m_5.prop|{{.*}}_5.sym
+; CHECK-LNL-EMPTY:
+
+; BMG does not support sg8 (=1) or sg64 (=2)
+; CHECK-BMG:      _intel_gpu_bmg_g21_0.prop|{{.*}}_0.sym
+; CHECK-BMG-NEXT: _intel_gpu_bmg_g21_3.prop|{{.*}}_3.sym
+; CHECK-BMG-NEXT: _intel_gpu_bmg_g21_4.prop|{{.*}}_4.sym
+; CHECK-BMG-NEXT: _intel_gpu_bmg_g21_5.prop|{{.*}}_5.sym
+; CHECK-BMG-EMPTY:
+
 target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
 target triple = "spir64-unknown-unknown"