Pinned Loading

1. ALU_sim ALU_sim Public

   Basic ALU simulator in HCS12 assembly.

   Assembly

2. bode bode Public

   Bode plot generator for continuous LTI transfer functions.

   Python

3. DRAMC DRAMC Public

   Behavioral architecture of a read/write cycle controller for a DRAM chip.

   VHDL 1

4. SDPM SDPM Public

   Serial data processing module design/implementation using VHDL.

   Tcl

5. SN74ALS561A SN74ALS561A Public

   Behavioral architecture of a TI SN74ALS561A chip.

   Tcl

6. I82C55A I82C55A Public

   Parallel I/O interface module design/implementation using VHDL.

   VHDL