Skip to content
View kdizzlle's full-sized avatar

Block or report kdizzlle

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
kdizzlle/README.md
  • 👋 Hi, I’m @kdizzlle
  • 🌱 I’m currently majoring in Computer Engineering at Cal Poly Pomona

Pinned Loading

  1. ece-3300L-verilog ece-3300L-verilog Public

    Verilog Digital Circuit Design Fall 2024 Cal Poly Pomona

    Tcl

  2. ece-3301L-microcontrollers ece-3301L-microcontrollers Public

    Microcontrollers Lab at Cal Poly Pomona Fall 2024

    Makefile