Litex add litespi flash and watchdog

.github/workflows/ci.yml

@@ -6,59 +6,39 @@ jobs:
   Bitstream-build:
     runs-on: ubuntu-22.04
     steps:
-      - uses: actions/checkout@v2
+      - uses: actions/checkout@v4
         with: 
           submodules: recursive
 
       - name: Install dependencies
         run: |
           sudo apt-get update
           sudo apt-get install -y python3-pip bzip2 cmake build-essential clang bison flex tcl-dev libffi-dev mercurial graphviz xdot pkg-config python3 libftdi-dev python3-dev libeigen3-dev zlib1g-dev
-          sudo apt update
           sudo apt-get install -y libboost-dev libboost-filesystem-dev libboost-thread-dev libboost-program-options-dev libboost-iostreams-dev libboost-dev libboost-system-dev libboost-python-dev libboost-filesystem-dev
-          curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s -- -y
-          ./install.sh
+          sudo apt-get install -y gcc-riscv64-unknown-elf
 
-      - name: Install yosys
+      - name: Install OSS CAD tools
         run: |
-          git clone https://github.com/YosysHQ/yosys.git
-          cd yosys
-          make config-gcc
-          make -j`nproc`
-          sudo make install
-          cd ..
-          rm -rf yosys
-
-      - name: Install prjoxide
-        run: |
-          git clone --recursive https://github.com/gatecat/prjoxide
-          cd prjoxide/libprjoxide
-          export PATH=$HOME/.cargo/bin:$PATH
-          cargo install --path prjoxide
-          cd ../../
-          rm -rf prjoxide
-
-      - name: Install nextpnr
-        run: |
-          git clone --recursive https://github.com/YosysHQ/nextpnr
-          cd nextpnr
-          cmake -DARCH=nexus -DOXIDE_INSTALL_PREFIX=$HOME/.cargo .
-          make -j`nproc`
-          sudo make install
-          cd ..
-          rm -rf nextpnr
+          curl -s https://api.github.com/repos/YosysHQ/oss-cad-suite-build/releases/latest \
+            | grep "browser_download_url.*oss-cad-suite-linux-x64-" \
+            | cut -d : -f 2,3 \
+            | tr -d \" \
+            | wget -qi -
+          tar -xf oss-cad-suite-linux-x64-*.tgz
+          rm -v oss-cad-suite-linux-x64-*.tgz
 
       - name: Build bitstream
         run: |
+          source oss-cad-suite/environment
           source ./init
-          pip3 install packaging
+          pip3 install packaging meson ninja
           echo $PATH
-          ./make.py --board=sdi_mipi_bridge --toolchain=oxide --build --csr-json csr.json
+          ./make.py --board=sdi_mipi_bridge --toolchain=oxide --build --csr-json csr.json --with_all
 
       - name: Generate dts and config
         run: ./third_party/litex/litex/tools/litex_json2dts_zephyr.py --dts overlay.dts --config overlay.config csr.json
 
-      - uses: actions/upload-artifact@v3
+      - uses: actions/upload-artifact@v4
         with:
           name: ${{github.job}}
           path: |
@@ -70,9 +50,9 @@ jobs:
     runs-on: ubuntu-22.04
     needs: Bitstream-build
     steps:
-      - uses: actions/checkout@v2
+      - uses: actions/checkout@v4
 
-      - uses: actions/download-artifact@v3
+      - uses: actions/download-artifact@v4
         with:
           name: Bitstream-build
 
@@ -85,9 +65,7 @@ jobs:
 
       - name: Download Zephyr SDK
         run: |
-          wget https://github.com/zephyrproject-rtos/sdk-ng/releases/download/v0.15.0/zephyr-sdk-0.15.0_linux-x86_64.tar.gz
-          tar xvf zephyr-sdk-0.15.0_linux-x86_64.tar.gz
-          rm -v zephyr-sdk-0.15.0_linux-x86_64.tar.gz
+          wget -q -O - https://github.com/zephyrproject-rtos/sdk-ng/releases/download/v0.16.8/zephyr-sdk-0.16.8_linux-x86_64.tar.xz | tar -J -xf -
 
       - name: Prepare Zephyr
         run: |
@@ -101,13 +79,13 @@ jobs:
 
       - name: Install Zephyr SDK
         run: |
-          cd zephyr-sdk-0.15.0/
+          cd zephyr-sdk-*
           ./setup.sh -h -t riscv64-zephyr-elf
           cd ../
 
       - name: Build Zephyr App
         run: |
-          export CMAKE_PREFIX_PATH=$PWD/zephyr-sdk-0.15.0
+          export ZEPHYR_SDK_INSTALL_DIR=$PWD
           cd zephyrproject/zephyr
           cat ../../Bitstream-build/overlay.config | xargs west build -b litex_vexriscv samples/philosophers/ -- -DDTC_OVERLAY_FILE= ../../Bitstream-build/overlay.dts
           cd ../../

.gitmodules

@@ -31,6 +31,9 @@
 [submodule "third_party/litex-boards"]
 	path = third_party/litex-boards
 	url = https://github.com/litex-hub/litex-boards.git
+[submodule "third_party/litespi"]
+	path = third_party/litespi
+	url = https://github.com/litex-hub/litespi.git
 [submodule "third_party/liteiclink"]
 	path = third_party/liteiclink
 	url = https://github.com/enjoy-digital/liteiclink.git

README.md

@@ -62,10 +62,12 @@ Build options
 | --with_i2s | Enable i2s |
 | --sys-clk-freq | System clock frequency |
 | --with_spi | Enable SPI |
+| --with_spi_flash | Enable SPI flash |
 | --with_i2c | Enable i2c |
 | --with_pwm | Enable PWM |
 | --spi-data-width | SPI data width |
 | --spi-clk-freq | SPI clock frequency |
+| --spi_flash_rate | SPI flash rate |
 | --with_mmcm | Enable MMCM |
 | --local-ip | local IP address |
 | --remote-ip | remote IP address |

init

@@ -1,7 +1,7 @@
 export PATH="${PWD}/third_party/litex/litex/tools:$PATH"
 export PATH="${PWD}/tools/conda/bin:$PATH"
 
-directories=(litedram liteeth liteiclink litepcie litesata litescope litevideo litex litex-boards litex-renode migen nmigen pythondata-cpu-vexriscv pythondata-software-compiler_rt pythondata-software-picolibc)
+directories=(litedram liteeth liteiclink litepcie litespi litesata litescope litevideo litex litex-boards litex-renode migen nmigen pythondata-cpu-vexriscv pythondata-software-compiler_rt pythondata-software-picolibc)
 
 for directory in "${directories[@]}";
 do

make.py

@@ -67,24 +67,44 @@ def main():
     parser.add_argument("--toolchain", default="symbiflow", help="FPGA toolchain - vivado, symbiflow or oxide (yosys+nextpnr).")
     parser.add_argument("--board", required=True, help="FPGA board")
     parser.add_argument("--build", action="store_true", help="build bitstream")
+    parser.add_argument("--flash", action="store_true", help="Flash bitstream.")
     parser.add_argument("--variant", default=None, help="FPGA board variant")
     parser.add_argument("--load", action="store_true", help="load bitstream (to SRAM). set path to bitstream")
+    parser.add_argument("--with_all", action="store_true", help="Enable all peripherals")
     parser.add_argument("--with_ethernet", action="store_true", help="Enable ethernet (Arty target only)")
+    parser.add_argument("--with_etherbone", action="store_true", help="Enable etherbone (Arty target only)")
     parser.add_argument("--with_i2s", action="store_true", help="Enable i2s (Arty target only)")
     parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
     parser.add_argument("--with_spi", action="store_true", help="Enable spi (Arty target only)")
+    parser.add_argument("--with_spi_flash", action="store_true", help="Enable spi flash (Arty target only)")
     parser.add_argument("--with_i2c", action="store_true", help="Enable i2c (Arty target only)")
     parser.add_argument("--with_pwm", action="store_true", help="Enable pwm (Arty target only)")
     parser.add_argument("--spi-data-width", type=int, default=8,      help="SPI data width (maximum transfered bits per xfer, Arty target only)")
     parser.add_argument("--spi-clk-freq",   type=int, default=1e6,    help="SPI clock frequency (Arty target only)")
+    parser.add_argument("--spi_flash_rate", default="1:1", help="SPI flash rate, can be 1:1 or 1:2 (Arty target only)")
     parser.add_argument("--with_mmcm", action="store_true", help="Enable mmcm (Arty target only)")
-    parser.add_argument("--local-ip", default="192.168.1.50", help="local IP address (Arty target only)")
+    parser.add_argument("--with_watchdog", action="store_true", help="Enable watchdog")
+    parser.add_argument("--watchdog_width", type=int, default=32, help="Watchdog width")
+    parser.add_argument("--watchdog_reset_delay", type=int, default=None, help="Watchdog reset delay")
+    parser.add_argument("--etherbone-ip", default="192.168.1.50", help="etherbone IP address (Arty target only)")
+    parser.add_argument("--local-ip", default="192.168.1.51", help="local IP address (Arty target only)")
     parser.add_argument("--remote-ip", default="192.168.1.100", help="remote IP address of TFTP server (Arty target only)")
     builder_args(parser)
     vivado_build_args(parser)
     oxide_args(parser)
     args = parser.parse_args()
 
+    if args.with_all:
+        args.with_ethernet = True
+        args.with_etherbone = True
+        args.with_i2s = True
+        args.with_spi = True
+        args.with_spi_flash = True
+        args.with_i2c = True
+        args.with_pwm = True
+        args.with_mmcm = True
+        args.with_watchdog = True
+
     if args.board == "all":
         board_names = list(supported_boards.keys())
     else:
@@ -108,15 +128,30 @@ def main():
 
         soc = SoCZephyr(board.soc_cls, **soc_kwargs)
 
+        if args.with_watchdog:
+            soc.add_watchdog(name="watchdog0" ,width=args.watchdog_width, reset_delay=args.watchdog_reset_delay)
+
         if board_name == "arty":
-            if args.with_ethernet:
-                soc.add_eth(local_ip=args.local_ip, remote_ip=args.remote_ip)
+            if args.with_ethernet or args.with_etherbone:
+                from liteeth.phy.mii import LiteEthPHYMII
+                soc.ethphy = LiteEthPHYMII(
+                    clock_pads = soc.platform.request("eth_clocks"),
+                    pads       = soc.platform.request("eth"))
+                if args.with_etherbone:
+                    soc.add_etherbone(phy=soc.ethphy, ip_address=args.etherbone_ip, with_ethmac=args.with_ethernet, ethmac_local_ip=args.local_ip, ethmac_remote_ip=args.remote_ip)
+                elif args.with_ethernet:
+                    soc.add_ethernet(phy=soc.ethphy, local_ip=args.local_ip, remote_ip=args.remote_ip)
             if args.with_mmcm:
                 soc.add_mmcm(board.mmcm_freq)
             if args.with_pwm:
                 soc.add_rgb_led()
             if args.with_spi:
-                soc.add_spi(args.spi_data_width, args.spi_clk_freq)
+                soc.add_spi_master(name="spi", data_width=args.spi_data_width, spi_clk_freq=args.spi_clk_freq)
+            if args.with_spi_flash:
+                from litespi.modules import S25FL128L
+                from litespi.opcodes import SpiNorFlashOpCodes as Codes
+                assert  args.spi_flash_rate in ["1:1", "1:2"]
+                soc.add_spi_flash(mode="4x", module=S25FL128L(Codes.READ_1_1_4), rate=args.spi_flash_rate, with_master=True)
             if args.with_i2c:
                 soc.add_i2c()
             if args.with_i2s:
@@ -139,6 +174,10 @@ def main():
 
         if args.load:
             board.load(soc, filename=os.path.join(build_dir, "gateware", board.bitstream_name + board.bitstream_ext))
+
+        if args.flash:
+            prog = soc.platform.create_programmer()
+            prog.flash(0, os.path.join(build_dir, "gateware", board.bitstream_name + board.bitstream_ext))
 
 if __name__ == "__main__":
     main()

soc_zephyr.py

@@ -49,6 +49,9 @@ class _SoCZephyr(soc_cls):
             "i2s_rx":     21, # addr: 0xe000a800
             "i2s_tx":     22, # addr: 0xe000b000
             "ddrphy":     23, # addr: 0xe000b800
+            "spiflash_core":   24, # addr: 0xe000c000
+            "spiflash_phy":    25, # addr: 0xe000c800
+            "watchdog0":  26, # addr: 0xe000d000
         }}
 
         interrupt_map = {**soc_cls.interrupt_map, **{
@@ -57,12 +60,14 @@ class _SoCZephyr(soc_cls):
             "ethmac":     3,
             "i2s_rx":     6,
             "i2s_tx":     7,
+            "watchdog0":  8,
         }}
 
         mem_map_zephyr = {
             "rom":          0x00000000,
             "sram":         0x01000000,
             "main_ram":     0x40000000,
+            "spiflash":     0x60000000,
             "ethmac":       0xb0000000,
             "i2s_rx":       0xb1000000,
             "i2s_tx":       0xb2000000,
@@ -79,10 +84,6 @@ def __init__(self, cpu_variant="standard", **kwargs):
                 **kwargs)
             soc_cls.mem_map.update(self.mem_map_zephyr)
 
-        def add_spi(self, data_width, spi_clk_freq):
-            spi_pads = self.platform.request("spi", 0)
-            self.submodules.spi = SPIMaster(spi_pads, data_width, self.clk_freq, spi_clk_freq)
-
         def add_rgb_led(self):
             rgb_led_pads = self.platform.request("rgb_led", 0)
             setattr(self.submodules, "rgb_led_r0", PWM(getattr(rgb_led_pads, 'r')))
@@ -142,49 +143,4 @@ def add_mmcm(self, freqs={}):
             self.mmcm.expose_drp()
             self.comb += self.mmcm.reset.eq(self.mmcm.drp_reset.re)
 
-        def add_eth(self, local_ip, remote_ip):
-            local_ip = local_ip.split(".")
-            remote_ip = remote_ip.split(".")
-
-            self.add_constant("LOCALIP1", int(local_ip[0]))
-            self.add_constant("LOCALIP2", int(local_ip[1]))
-            self.add_constant("LOCALIP3", int(local_ip[2]))
-            self.add_constant("LOCALIP4", int(local_ip[3]))
-
-            self.add_constant("REMOTEIP1", int(remote_ip[0]))
-            self.add_constant("REMOTEIP2", int(remote_ip[1]))
-            self.add_constant("REMOTEIP3", int(remote_ip[2]))
-            self.add_constant("REMOTEIP4", int(remote_ip[3]))
-            self.submodules.ethphy = LiteEthPHYMII(
-                clock_pads = self.platform.request("eth_clocks"),
-                pads       = self.platform.request("eth"))
-            phy = self.ethphy
-            # Imports
-            from liteeth.mac import LiteEthMAC
-            # MAC
-            ethmac = LiteEthMAC(
-                phy=phy,
-                dw=32,
-                interface="wishbone",
-                endianness=self.cpu.endianness)
-
-            self.submodules.ethmac = ethmac
-            name="ethmac"
-            ethmac_region=SoCRegion(origin=self.mem_map_zephyr.get(name, None), size=0x2000, cached=False)
-            self.bus.add_slave(name=name, slave=ethmac.bus, region=ethmac_region)
-
-            # Timing constraints
-            if hasattr(phy, "crg"):
-                eth_rx_clk = phy.crg.cd_eth_rx.clk
-                eth_tx_clk = phy.crg.cd_eth_tx.clk
-            else:
-                eth_rx_clk = phy.cd_eth_rx.clk
-                eth_tx_clk = phy.cd_eth_tx.clk
-            self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
-            self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
-            self.platform.add_false_path_constraints(
-                self.crg.cd_sys.clk,
-                eth_rx_clk,
-                eth_tx_clk)
-
     return _SoCZephyr(**kwargs)