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[rtl] Fix zero value in FPGA RF #236

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[rtl] Fix zero value in FPGA RF

[rtl] Fix zero value in FPGA RF #236

Triggered via pull request November 18, 2024 12:01
@nasahlpanasahlpa
opened #2224
nasahlpa:ibex_fpga_regfile
Status Success
Total duration 11m 33s
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on: pull_request
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10 errors
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The RISC-V compliance test suite failed for rv32i
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Expected failure for rv32i, see lowrisc/ibex#100 more more information.
Run quality checks (Lint and DV)
The RISC-V compliance test suite failed for rv32i
Run quality checks (Lint and DV)
Expected failure for rv32i, see lowrisc/ibex#100 more more information.
Run quality checks (Lint and DV)
The RISC-V compliance test suite failed for rv32i
Run quality checks (Lint and DV)
Expected failure for rv32i, see lowrisc/ibex#100 more more information.
Run quality checks (Lint and DV)
The RISC-V compliance test suite failed for rv32i
Run quality checks (Lint and DV)
Expected failure for rv32i, see lowrisc/ibex#100 more more information.
Run quality checks (Lint and DV)
The RISC-V compliance test suite failed for rv32i
Run quality checks (Lint and DV)
Expected failure for rv32i, see lowrisc/ibex#100 more more information.