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Flush pipeline when PMP CSRs are cleared #2195

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marnovandermaas
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Closes: #2193

@mndstrmr
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This is my suggested solution, but I think it's wrong: Doesn't this prevent the else case ever being entered? Indeed was the else case ever correct? It would previously not be entered e.g. on a WRITE to a debug register, which it clearly should be.

I think the if and else should be merged, and the inner if statements merged into their parents, something like the below:

assign csr_pipe_flush = 
    csr_op_en_o == 1'b1 && csr_op_o != CSR_OP_READ && (
    	csr_num_e'(instr_rdata_i[31:20]) == CSR_MSTATUS   ||
     	csr_num_e'(instr_rdata_i[31:20]) == CSR_MIE       ||
      	csr_num_e'(instr_rdata_i[31:20]) == CSR_MSECCFG   ||
      	// To catch all PMPCFG/PMPADDR registers, get the shared top most 7 bits.
      	instr_rdata_i[31:25] == 7'h1D 		  	  ||
    	csr_num_e'(instr_rdata_i[31:20]) == CSR_DCSR      ||
	csr_num_e'(instr_rdata_i[31:20]) == CSR_DPC       ||
	csr_num_e'(instr_rdata_i[31:20]) == CSR_DSCRATCH0 ||
	csr_num_e'(instr_rdata_i[31:20]) == CSR_DSCRATCH1
    );

@nbdd0121
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Very good point. Although it seems that the else case is already not being entered when doing full CSR write?

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@GregAC GregAC left a comment

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I wanted to discuss different ways to approach this so please do not merge this for now.

@nbdd0121 nbdd0121 self-requested a review July 24, 2024 12:44
@GregAC
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GregAC commented Jul 24, 2024

I also don't want to make any RTL changes to Ibex until I've sorted the OT earlgrey release branch

@marnovandermaas
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Closing this PR because it probably needs a different solution.

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Pipeline not being flushed on PMP register clears
4 participants