[sival,otbn] Add CW340 exec. env for otbn_mem_scramble_test

Closes #20119. Signed-off-by: Pascal Nasahl <[email protected]>
lowRISC · Nov 15, 2024 · c3ed16d · c3ed16d
1 parent ef394b7
commit c3ed16d
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/sw/device/tests/BUILD b/sw/device/tests/BUILD
@@ -2510,14 +2510,14 @@ opentitan_test(
     name = "otbn_mem_scramble_test",
     srcs = ["otbn_mem_scramble_test.c"],
     exec_env = dicts.add(
-        EARLGREY_TEST_ENVS,
         EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
         {
+            "//hw/top_earlgrey:fpga_cw340_sival": None,
             "//hw/top_earlgrey:silicon_creator": None,
+            "//hw/top_earlgrey:sim_dv": None,
+            "//hw/top_earlgrey:sim_verilator": None,
         },
     ),
-    # TODO(#12486) [bazel] targets in sw/device/tests failing on cw310 and verilator when built by bazel
-    fpga = fpga_params(tags = ["broken"]),
     verilator = verilator_params(timeout = "long"),
     deps = [
         "//hw/top_earlgrey/sw/autogen:top_earlgrey",