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[rv_core_ibex, top_earlgrey] Enable SecureIbex for CW340 #25146

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2 changes: 1 addition & 1 deletion hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv
Original file line number Diff line number Diff line change
Expand Up @@ -1079,9 +1079,9 @@ module chip_earlgrey_cw310 #(
.KeymgrKmacEnMasking(0),
.SecKmacCmdDelay(0),
.SecKmacIdleAcceptSwMsg(1'b0),
.RvCoreIbexSecureIbex(0),
.RomCtrlBootRomInitFile(BootRomInitFile),
.RvCoreIbexRegFile(ibex_pkg::RegFileFPGA),
.RvCoreIbexSecureIbex(0),
.SramCtrlMainInstrExec(1),
.PinmuxAonTargetCfg(PinmuxTargetCfg)
) top_earlgrey (
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2 changes: 1 addition & 1 deletion hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw340.sv
Original file line number Diff line number Diff line change
Expand Up @@ -1063,9 +1063,9 @@ module chip_earlgrey_cw340 #(
.KmacEnMasking(1),
.KmacSwKeyMasked(1),
.KeymgrKmacEnMasking(1),
.RvCoreIbexSecureIbex(1),
.RomCtrlBootRomInitFile(BootRomInitFile),
.RvCoreIbexRegFile(ibex_pkg::RegFileFPGA),
.RvCoreIbexSecureIbex(0),
.SramCtrlMainInstrExec(1),
.PinmuxAonTargetCfg(PinmuxTargetCfg)
) top_earlgrey (
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4 changes: 3 additions & 1 deletion hw/top_earlgrey/templates/chiplevel.sv.tpl
Original file line number Diff line number Diff line change
Expand Up @@ -1158,6 +1158,7 @@ module chip_${top["name"]}_${target["name"]} #(
.SecAesAllowForcingMasks(1'b1),
.SecAesSkipPRNGReseeding(1'b1),
.UsbdevStub(1'b1),
.RvCoreIbexSecureIbex(0),
% else:
.SecAesMasking(1'b0),
.SecAesSBoxImpl(aes_pkg::SBoxImplLut),
Expand All @@ -1178,16 +1179,17 @@ module chip_${top["name"]}_${target["name"]} #(
.KmacEnMasking(1),
.KmacSwKeyMasked(1),
.KeymgrKmacEnMasking(1),
.RvCoreIbexSecureIbex(1),
% elif target["name"] == "cw310":
.KmacEnMasking(0),
.KmacSwKeyMasked(1),
.KeymgrKmacEnMasking(0),
.SecKmacCmdDelay(0),
.SecKmacIdleAcceptSwMsg(1'b0),
.RvCoreIbexSecureIbex(0),
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You probably also should add that for the cw305.

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Ah thanks, done.

% endif
.RomCtrlBootRomInitFile(BootRomInitFile),
.RvCoreIbexRegFile(ibex_pkg::RegFileFPGA),
.RvCoreIbexSecureIbex(0),
.SramCtrlMainInstrExec(1),
.PinmuxAonTargetCfg(PinmuxTargetCfg)
) top_${top["name"]} (
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2 changes: 1 addition & 1 deletion hw/vendor/lowrisc_ibex/rtl/ibex_top.sv
Original file line number Diff line number Diff line change
Expand Up @@ -148,7 +148,7 @@ module ibex_top import ibex_pkg::*; #(
localparam bit Lockstep = SecureIbex;
localparam bit ResetAll = Lockstep;
localparam bit DummyInstructions = SecureIbex;
localparam bit RegFileECC = SecureIbex;
localparam bit RegFileECC = 1'b0;
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This change should be removed before merging this.

localparam bit RegFileWrenCheck = SecureIbex;
localparam bit RegFileRdataMuxCheck = SecureIbex;
localparam int unsigned RegFileDataWidth = RegFileECC ? 32 + 7 : 32;
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6 changes: 3 additions & 3 deletions sw/device/tests/BUILD
Original file line number Diff line number Diff line change
Expand Up @@ -2518,14 +2518,14 @@ opentitan_test(
name = "otbn_mem_scramble_test",
srcs = ["otbn_mem_scramble_test.c"],
exec_env = dicts.add(
EARLGREY_TEST_ENVS,
EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
{
"//hw/top_earlgrey:fpga_cw340_sival": None,
"//hw/top_earlgrey:silicon_creator": None,
"//hw/top_earlgrey:sim_dv": None,
"//hw/top_earlgrey:sim_verilator": None,
},
),
# TODO(#12486) [bazel] targets in sw/device/tests failing on cw310 and verilator when built by bazel
fpga = fpga_params(tags = ["broken"]),
verilator = verilator_params(timeout = "long"),
deps = [
"//hw/top_earlgrey/sw/autogen:top_earlgrey",
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