Earlgrey-PROD.M6

The main goal of the Earlgrey-PROD.M6 milestone is to triage potential ECO candidates identified after Earlgrey-PROD-M5, and to implement any approved and final ECOs. With Earlgrey-PROD.M6, the physical design reached its final state for the production tapeout.

Since Earlgrey-PROD.M5, the following changes with direct silicon impact have been made:

• The pull-down of the IOC8 pad used for sampling TAP strap 0 has been enabled at reset (#24604, #24624). This is to ensure the pad gets sampled as 0 unless driven to 1 from an external source.
• To alleviate timing pressure, the scrambling of the main SRAM has been changed back to again use 2 PRINCE cipher half rounds (2 half rounds = 5 effective rounds) as in the engineering sample (#24447, #24378).
• To enable timing closure, ECC related feedthrough paths in Ibex have been removed (#2206, #24403, #24383).
• Readback errors inside the main and retention SRAM controllers are now always signaled as alerts (#24679, #24702)
• The storage error output signals of the shadowed measurement control registers for the MAIN clock domain are now registered to avoid combinatorial glitches on those signals, thereby preventing potential CDC issues (#24622).
• The sd_en_o output of both SPI_HOST instances got de-glitched to enable timing closure (#24501, #24500).
• The ROM_EXT immutable section configuration in ROM has been fixed to work with address translation (#24415, #24417).