cpu/drcbearm64.cpp: Optimise load/store and call generation

[cuavas]

This should implement some of the optimisations previously discussed for AArch64 code generation:

• bl displacement is in words
• The emit_*_mem functions know the operand size, so they can pass the corresponding shift to emit_ldr_str_base_mem rather than trying to calculate it after the fact
• An immediate load/store offset can be either a 9-bit signed byte offset or an unsigned 12-bit element offset
• An unsigned 12-bit element offset can always reach an entire page, so the page-relative access can always be done in two instructions

And one bug fix:

• AArch64 doesn’t allow a variable left shift for a register offset, it only allows zero or the element size, so there’s no point testing intermediate shift values.

@987123879113 and/or @rb6502 can you check this out and test it?

[cuavas]

I just realised the 12-bit unsigned offset can only reach an entire page for aligned accesses. Hopefully the vast majority of accesses are aligned anyway.

There’s still one form of ldr we aren’t trying to use – the PC-relative form with a 19-bit signed displacement in words ±1MB reach). It can only be used to load a word or doubleword (not a byte or halfword, or a floating-point type), and there’s no equivalent str form.

[987123879113]

Code looks fine to me. I ran it through a few games + the tester and no issues from what I can tell.