MIPS54cpu-in-verilog

单周期CPU 频率可达到65M

实现MIPS架构CPU的54条基本指令

CPU架构

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
54cpu.png		54cpu.png
54指令CPU实验指导书.pdf		54指令CPU实验指导书.pdf
DIV.v		DIV.v
DIVU.v		DIVU.v
HL.v		HL.v
MULT.v		MULT.v
README.md		README.md
Regfiles.v		Regfiles.v
alu.v		alu.v
control.v		control.v
cp0.v		cp0.v
cpu_tb.v		cpu_tb.v
dmem.v		dmem.v
io_sel.v		io_sel.v
multu.v		multu.v
pcreg.v		pcreg.v
sccomp_dataflow.v		sccomp_dataflow.v
sccpu.v		sccpu.v
seg7x16.v		seg7x16.v
sw_mem_sel.v		sw_mem_sel.v

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