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SDP MSPI driver #18893

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merged 5 commits into from
Jan 15, 2025
Merged

SDP MSPI driver #18893

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01eb761
drivers: mspi: Add SDP MSPI driver
jaz1-nordic Nov 18, 2024
a92b026
snippets: sdp: mspi: Add SDP MSPI snippet files
jaz1-nordic Nov 18, 2024
6f35a51
sysbuild: sdp: Add SDP MSPI to cmake
jaz1-nordic Nov 18, 2024
80c79cd
applications: sdp: mspi: Add IPC solution to SDP MSPI application
jaz1-nordic Nov 27, 2024
e7aa8d4
tests: drivers: mspi: add SDP MSPI API test configuration
jaz1-nordic Dec 13, 2024
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3 changes: 3 additions & 0 deletions CODEOWNERS
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Original file line number Diff line number Diff line change
Expand Up @@ -294,6 +294,7 @@
/drivers/gpio/ @nrfconnect/ncs-co-drivers @nrfconnect/ncs-ll-ursus
/drivers/hw_cc3xx/ @nrfconnect/ncs-co-drivers @nrfconnect/ncs-aegir
/drivers/mpsl/ @nrfconnect/ncs-co-drivers @nrfconnect/ncs-dragoon
/drivers/mspi/ @nrfconnect/ncs-co-drivers @nrfconnect/ncs-ll-ursus
/drivers/net/ @nrfconnect/ncs-co-drivers @doki-nordic
/drivers/serial/ @nrfconnect/ncs-co-drivers @nordic-krch
/drivers/sensor/bh1749/ @nrfconnect/ncs-co-drivers @nrfconnect/ncs-cia
Expand Down Expand Up @@ -330,6 +331,7 @@
/include/drivers/flash/ @nrfconnect/ncs-co-drivers
/include/drivers/gpio/ @nrfconnect/ncs-co-drivers @nrfconnect/ncs-ll-ursus
/include/drivers/bme68x_iaq.h @nrfconnect/ncs-co-drivers @nrfconnect/ncs-cia
/include/drivers/mspi/nrfe_mspi.h @nrfconnect/ncs-co-drivers @nrfconnect/ncs-ll-ursus
/include/drivers/sensor_sim.h @nrfconnect/ncs-co-drivers @nrfconnect/ncs-cia
/include/drivers/sensor_stub.h @nrfconnect/ncs-co-drivers @nrfconnect/ncs-cia
/include/emds/ @balaklaka @nrfconnect/ncs-paladin
Expand Down Expand Up @@ -670,6 +672,7 @@
/scripts/print_docker_image.sh @nrfconnect/ncs-ci
/scripts/print_toolchain_checksum.sh @nrfconnect/ncs-ci
/scripts/sdp/ @nrfconnect/ncs-ll-ursus
/scripts/twister/alt/zephyr/tests/drivers/mspi/api/testcase.yaml @nrfconnect/ncs-ll-ursus

/scripts/docker/*.rst @nrfconnect/ncs-doc-leads
/scripts/hid_configurator/*.rst @nrfconnect/ncs-si-bluebagel-doc
Expand Down
52 changes: 52 additions & 0 deletions applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay
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Expand Up @@ -4,6 +4,58 @@
* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
*/

/ {
soc {
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;

sram_tx: memory@2003c000 {
reg = <0x2003c000 0x0800>;
};

sram_rx: memory@2003c800 {
reg = <0x2003c800 0x0800>;
};
};
};

ipc {
ipc0: ipc0 {
compatible = "zephyr,ipc-icmsg";
tx-region = <&sram_tx>;
rx-region = <&sram_rx>;
mboxes = <&cpuflpr_vevif_rx 16>, <&cpuflpr_vevif_tx 20>;
mbox-names = "rx", "tx";
status = "okay";
};
};
};

&cpuflpr_rram {
reg = <0x17a000 DT_SIZE_K(12)>;
};

&cpuflpr_code_partition {
reg = <0x0 DT_SIZE_K(12)>;
};

&cpuflpr_sram {
reg = <0x2003d000 DT_SIZE_K(12)>;
ranges = <0x0 0x2003d000 0x3000>;
};

&cpuflpr_vevif_rx {
status = "okay";
interrupts = <16 NRF_DEFAULT_IRQ_PRIORITY>;
nordic,tasks = <1>;
nordic,tasks-mask = <0x00010000>;
};

&cpuflpr_vevif_tx {
status = "okay";
};

&gpio0 {
status = "disabled";
};
Expand Down
6 changes: 3 additions & 3 deletions applications/sdp/mspi/prj.conf
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Original file line number Diff line number Diff line change
@@ -1,3 +1,3 @@
CONFIG_MBOX=n
CONFIG_IPC_SERVICE=n
CONFIG_IPC_SERVICE_BACKEND_ICMSG=n
CONFIG_MBOX=y
CONFIG_IPC_SERVICE=y
CONFIG_IPC_SERVICE_BACKEND_ICMSG=y
2 changes: 1 addition & 1 deletion applications/sdp/mspi/sample.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ common:
integration_platforms:
- nrf54l15dk/nrf54l15/cpuflpr
tests:
applications.sdp.mspi.icmsg:
applications.sdp.mspi:
build_only: true
sysbuild: true
platform_allow: nrf54l15dk/nrf54l15/cpuflpr
Expand Down
46 changes: 26 additions & 20 deletions applications/sdp/mspi/src/hrt/hrt.c
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Original file line number Diff line number Diff line change
Expand Up @@ -22,12 +22,10 @@ void write_single_by_word(volatile struct hrt_ll_xfer xfer_ll_params)
NRFX_ASSERT(xfer_ll_params.word_size <= MAX_WORD_SIZE);
/* Configuration step */
dir = nrf_vpr_csr_vio_dir_get();

nrf_vpr_csr_vio_dir_set(dir | PIN_DIR_OUT_MASK(D0_PIN));
nrf_vpr_csr_vio_dir_set(dir | PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ0_PIN_NUMBER)));

out = nrf_vpr_csr_vio_out_get();

nrf_vpr_csr_vio_out_set(out | PIN_OUT_LOW_MASK(D0_PIN));
nrf_vpr_csr_vio_out_set(out | PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ0_PIN_NUMBER)));

nrf_vpr_csr_vio_mode_out_set(&out_mode);
nrf_vpr_csr_vio_mode_in_buffered_set(NRF_VPR_CSR_VIO_MODE_IN_CONTINUOUS);
Expand Down Expand Up @@ -59,9 +57,9 @@ void write_single_by_word(volatile struct hrt_ll_xfer xfer_ll_params)

/* Enable CS */
out = nrf_vpr_csr_vio_out_get();
out &= ~PIN_OUT_HIGH_MASK(CS_PIN);
out |= xfer_ll_params.ce_enable_state ? PIN_OUT_HIGH_MASK(CS_PIN)
: PIN_OUT_LOW_MASK(CS_PIN);
out &= ~PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
out |= xfer_ll_params.ce_enable_state ? PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER))
: PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
nrf_vpr_csr_vio_out_set(out);

/* Start counter */
Expand All @@ -84,9 +82,11 @@ void write_single_by_word(volatile struct hrt_ll_xfer xfer_ll_params)
/* Disable CS */
if (!xfer_ll_params.ce_hold) {
out = nrf_vpr_csr_vio_out_get();
out &= ~(PIN_OUT_HIGH_MASK(CS_PIN) | PIN_OUT_HIGH_MASK(SCLK_PIN));
out |= xfer_ll_params.ce_enable_state ? PIN_OUT_LOW_MASK(CS_PIN)
: PIN_OUT_HIGH_MASK(CS_PIN);
out &= ~(PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) |
PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER)));
out |= xfer_ll_params.ce_enable_state
? PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER))
: PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
nrf_vpr_csr_vio_out_set(out);
}

Expand All @@ -109,13 +109,17 @@ void write_quad_by_word(volatile struct hrt_ll_xfer xfer_ll_params)
/* Configuration step */
dir = nrf_vpr_csr_vio_dir_get();

nrf_vpr_csr_vio_dir_set(dir | PIN_DIR_OUT_MASK(D0_PIN) | PIN_DIR_OUT_MASK(D1_PIN) |
PIN_DIR_OUT_MASK(D2_PIN) | PIN_DIR_OUT_MASK(D3_PIN));
nrf_vpr_csr_vio_dir_set(dir | PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ0_PIN_NUMBER)) |
PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ1_PIN_NUMBER)) |
PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ2_PIN_NUMBER)) |
PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ3_PIN_NUMBER)));

out = nrf_vpr_csr_vio_out_get();

nrf_vpr_csr_vio_out_set(out | PIN_OUT_LOW_MASK(D0_PIN) | PIN_OUT_LOW_MASK(D1_PIN) |
PIN_OUT_LOW_MASK(D2_PIN) | PIN_OUT_LOW_MASK(D3_PIN));
nrf_vpr_csr_vio_out_set(out | PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ0_PIN_NUMBER)) |
PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ1_PIN_NUMBER)) |
PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ2_PIN_NUMBER)) |
PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ3_PIN_NUMBER)));

nrf_vpr_csr_vio_mode_out_set(&out_mode);
nrf_vpr_csr_vio_mode_in_buffered_set(NRF_VPR_CSR_VIO_MODE_IN_CONTINUOUS);
Expand Down Expand Up @@ -147,9 +151,9 @@ void write_quad_by_word(volatile struct hrt_ll_xfer xfer_ll_params)

/* Enable CS */
out = nrf_vpr_csr_vio_out_get();
out &= ~PIN_OUT_HIGH_MASK(CS_PIN);
out |= xfer_ll_params.ce_enable_state ? PIN_OUT_HIGH_MASK(CS_PIN)
: PIN_OUT_LOW_MASK(CS_PIN);
out &= ~PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
out |= xfer_ll_params.ce_enable_state ? PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER))
: PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
nrf_vpr_csr_vio_out_set(out);

/* Start counter */
Expand All @@ -171,9 +175,11 @@ void write_quad_by_word(volatile struct hrt_ll_xfer xfer_ll_params)
/* Disable CS */
if (!xfer_ll_params.ce_hold) {
out = nrf_vpr_csr_vio_out_get();
out &= ~(PIN_OUT_HIGH_MASK(CS_PIN) | PIN_OUT_HIGH_MASK(SCLK_PIN));
out |= xfer_ll_params.ce_enable_state ? PIN_OUT_LOW_MASK(CS_PIN)
: PIN_OUT_HIGH_MASK(CS_PIN);
out &= ~(PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) |
PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER)));
out |= xfer_ll_params.ce_enable_state
? PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER))
: PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
nrf_vpr_csr_vio_out_set(out);
}

Expand Down
8 changes: 1 addition & 7 deletions applications/sdp/mspi/src/hrt/hrt.h
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Expand Up @@ -9,13 +9,7 @@

#include <stdint.h>
#include <stdbool.h>

#define SCLK_PIN 0
#define D0_PIN 1
#define D1_PIN 2
#define D2_PIN 3
#define D3_PIN 4
#define CS_PIN 5
#include <drivers/mspi/nrfe_mspi.h>
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I think there could be a separate header file for pin numbers/pin translation. I am not a fan of including the whole nrfe_mspi.h here, HRT does not need to know FLPR response struct, for example.
However, I guess the pin numbers/pin translation can be changed in the future when pin checking is added, so it can stay as it is for now.


/* Max word size. */
#define MAX_WORD_SIZE NRF_VPR_CSR_VIO_SHIFT_CNT_OUT_BUFFERED_MAX
Expand Down
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