power: apply change to save power

KRKNWK-19506 adjust configuration to improve power consumption on nrf54 Co-authored-by: Krzysztof Taborowski <[email protected]> Signed-off-by: Robert Gałat <[email protected]>
nrfconnect · Oct 23, 2024 · bffce86 · bffce86
1 parent 21fb2f2
commit bffce86
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Showing 10 changed files with 110 additions and 56 deletions.
diff --git a/samples/sid_end_device/Kconfig.sysbuild b/samples/sid_end_device/Kconfig.sysbuild
@@ -44,8 +44,6 @@ config NETCORE_APP_UPDATE
 config DFU_MULTI_IMAGE_PACKAGE_NET
 	default y
 
-endif # BOOTLOADER_MCUBOOT
-
 endif # (BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP)
 
 config PM_EXTERNAL_FLASH_MCUBOOT_SECONDARY
@@ -55,4 +53,6 @@ config PM_EXTERNAL_FLASH_MCUBOOT_SECONDARY
 config PM_MCUBOOT_PAD
 	default 0x800
 
+endif # BOOTLOADER_MCUBOOT
+
 source "${ZEPHYR_BASE}/share/sysbuild/Kconfig"
diff --git a/samples/sid_end_device/boards/nrf52840dk_nrf52840.overlay b/samples/sid_end_device/boards/nrf52840dk_nrf52840.overlay
@@ -16,7 +16,7 @@
 	nrfx_spi_gpios{
 		compatible = "gpio-keys";
 		nrfx_spi_sck: sck {
-			gpios = <&gpio1 0xF GPIO_ACTIVE_LOW>;
+			gpios = <&gpio1 0xF GPIO_ACTIVE_HIGH>;
 			label = "spi_sck";
 		};
 		nrfx_spi_miso: miso {
@@ -28,7 +28,7 @@
 			label = "spi_mosi";
 		};
 		nrfx_spi_cs: cs {
-			gpios = <&gpio1 0x8 GPIO_ACTIVE_HIGH>;
+			gpios = <&gpio1 0x8 GPIO_ACTIVE_LOW>;
 			label = "spi_cs";
 		};
 	};

diff --git a/samples/sid_end_device/boards/nrf54l15dk_nrf54l15_cpuapp.conf b/samples/sid_end_device/boards/nrf54l15dk_nrf54l15_cpuapp.conf
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2024 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+
+CONFIG_POWEROFF=y
diff --git a/samples/sid_end_device/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/samples/sid_end_device/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
@@ -31,9 +31,6 @@
 			label = "semtech_sx1262 DIO1";
 		};
 	};
-
-	// Use watchdog wdt31 as the application watchdog
-	watchdog0 = &wdt31;
 };
 
 sid_semtech: &spi30 {
@@ -46,7 +43,6 @@ sid_semtech: &spi30 {
 	clock-frequency = <DT_FREQ_M(8)>;
 };
 
-// restore full RRAM and SRAM space - by default some parts are dedicated to FLRP
 &cpuapp_rram {
 	reg = <0x0 DT_SIZE_K(1524)>;
 };
@@ -75,23 +71,22 @@ sid_semtech: &spi30 {
 	};
 };
 
-&gpio0 {
-	status = "okay";
+&adc {
+	status = "disabled";
 };
-
-&gpio1 {
-	status = "okay";
+&uart21 {
+	status = "disabled";
 };
-
-&gpio2 {
-	status = "okay";
+&pwm20 {
+	status = "disabled";
 };
-
-&wdt31 {
-	status = "okay";
+&i2c20 {
+	status = "disabled";
 };
-
-&mx25r64 {
+&spi20 {
+	status = "disabled";
+};
+&spi22 {
 	status = "disabled";
 };
 

diff --git a/samples/sid_end_device/prj_release.conf b/samples/sid_end_device/prj_release.conf
@@ -18,6 +18,9 @@ CONFIG_SERIAL=n
 CONFIG_SHELL=n
 CONFIG_CONSOLE=n
 CONFIG_UART_CONSOLE=n
+CONFIG_BOOT_BANNER=n
+CONFIG_NCS_BOOT_BANNER=n
+CONFIG_PRINTK=n
 CONFIG_ASSERT=n
 CONFIG_ASSERT_VERBOSE=n
 CONFIG_ASSERT_NO_FILE_INFO=y

diff --git a/samples/sid_end_device/sysbuild/mcuboot/boards/nrf54l15dk_nrf54l15_cpuapp.conf b/samples/sid_end_device/sysbuild/mcuboot/boards/nrf54l15dk_nrf54l15_cpuapp.conf
@@ -11,6 +11,13 @@ CONFIG_FPROTECT=n
 # TODO: Workaround, disable memory guard to avoid false faults in application after boot
 CONFIG_HW_STACK_PROTECTION=n
 
+# Currently, without tickless kernel, the SYSCOUNTER value after the software
+# reset is not set properly and due to that the first system interrupt is not called
+# in the proper time - the SYSCOUNTER value is set to the value from before
+# reset + 1. Hence, the reboot time increases more and more.
+# To avoid it enable tickles kernel for mcuboot.
+CONFIG_TICKLESS_KERNEL=y
+
 CONFIG_BOOT_WATCHDOG_FEED=n
 
 # Disable all debug features
@@ -28,6 +35,7 @@ CONFIG_PRINTK=n
 CONFIG_PRINTK_SYNC=n
 CONFIG_THREAD_NAME=n
 CONFIG_BOOT_BANNER=n
+CONFIG_NCS_BOOT_BANNER=n
 
 CONFIG_PM_OVERRIDE_EXTERNAL_DRIVER_CHECK=y
 
@@ -38,17 +46,12 @@ CONFIG_SPI_NOR=n
 CONFIG_NORDIC_QSPI_NOR=n
 CONFIG_MULTITHREADING=n
 
+# Others
 CONFIG_PM_OVERRIDE_EXTERNAL_DRIVER_CHECK=y
 
 
 # Workaroud: fprotect and watchdog feed
 # are not supported in NCS v2.6.0
 CONFIG_FPROTECT=n
 CONFIG_BOOT_WATCHDOG_FEED=n
-
-# Currently, without tickless kernel, the SYSCOUNTER value after the software
-# reset is not set properly and due to that the first system interrupt is not called
-# in the proper time - the SYSCOUNTER value is set to the value from before
-# reset + 1. Hence, the reboot time increases more and more.
-# To avoid it enable tickles kernel for mcuboot.
-CONFIG_TICKLESS_KERNEL=y
+CONFIG_POWEROFF=y
diff --git a/samples/sid_end_device/sysbuild/mcuboot/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/samples/sid_end_device/sysbuild/mcuboot/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
@@ -15,9 +15,34 @@
 	ranges = <0x0 0x20000000  0x40000>;
 };
 
- /* Disable the external flash, as it's not needed
-    for the configuration with secondary slot residing
-    in the internal MRAM. */
+&adc {
+	status = "disabled";
+};
+&uart21 {
+	status = "disabled";
+};
+&pwm20 {
+	status = "disabled";
+};
+&i2c20 {
+	status = "disabled";
+};
+&spi00 {
+	status = "disabled";
+};
+&spi20 {
+	status = "disabled";
+};
+&spi21 {
+	status = "disabled";
+};
+&spi22 {
+	status = "disabled";
+};
+
+/* Disable the external flash, as it's not needed
+for the configuration with secondary slot residing
+in the internal MRAM. */
 &mx25r64 {
 	status = "disabled";
 };
diff --git a/samples/sid_end_device/sysbuild/mcuboot/prj.conf b/samples/sid_end_device/sysbuild/mcuboot/prj.conf
@@ -21,13 +21,15 @@ CONFIG_MINIMAL_LIBC=y
 
 # Disable logs
 CONFIG_NCS_BOOT_BANNER=n
+CONFIG_BOOT_BANNER=n
 CONFIG_CONSOLE=n
 CONFIG_SERIAL=n
 CONFIG_UART_CONSOLE=n
+CONFIG_CONSOLE_HANDLER=n
 CONFIG_USE_SEGGER_RTT=n
 CONFIG_LOG=n
-CONFIG_CONSOLE_HANDLER=n
-CONFIG_BOOT_BANNER=n
+CONFIG_PRINTK=n
+CONFIG_ASSERT=n
 
 # Bootloader size optimization
 CONFIG_RESET_ON_FATAL_ERROR=n

diff --git a/subsys/sal/sid_pal/src/sid_gpio_utils.c b/subsys/sal/sid_pal/src/sid_gpio_utils.c
@@ -50,7 +50,7 @@ void sid_gpio_utils_clear_register(void)
 	memset(&ctx, 0, sizeof(ctx));
 }
 
-uint32_t find_gpio_in_register(struct gpio_dt_spec gpio_from_dts)
+static uint32_t find_gpio_in_register(struct gpio_dt_spec gpio_from_dts)
 {
 	for (uint32_t i = 0; i < ctx.next_free_slot; i++) {
 		if (ctx.supported_pins[i].gpio.port == gpio_from_dts.port &&

diff --git a/tests/functional/spi_bus/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/tests/functional/spi_bus/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
@@ -4,62 +4,77 @@
  * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
  */
 
-/{
+ /{
+	aliases {
+		state-notifier-connected = &led0;
+		state-notifier-time-sync = &led1;
+		state-notifier-registered = &led2;
+		state-notifier-working = &led3;
+	};
+
 	semtech_sx1262_gpios{
 		compatible = "gpio-keys";
-		semtech_sx1262_cs: cs {
-			gpios = <&gpio2 0xa GPIO_PULL_UP>;
-			label = "semtech_sx1262 CS";
-		};
 		semtech_sx1262_reset_gpios: reset {
-			gpios = <&gpio0 0x2 (GPIO_ACTIVE_LOW|GPIO_PULL_UP)>;
+			gpios = <&gpio2 8  (GPIO_ACTIVE_LOW|GPIO_PULL_UP)>;
 			label = "semtech_sx1262 Reset";
 		};
 		semtech_sx1262_busy_gpios: busy {
-			gpios = <&gpio0 0x0 0x0>;
+			gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH)>;
 			label = "semtech_sx1262 Busy";
 		};
 		semtech_sx1262_antenna_enable_gpios: antena_enable {
-			gpios = <&gpio0 0x1 0x0>;
+			gpios = <&gpio2 10 (GPIO_ACTIVE_HIGH)>;
 			label = "semtech_sx1262 Antena Enable";
 		};
 		semtech_sx1262_dio1_gpios: dio1 {
-			gpios = <&gpio0 0x3  0x0>;
+			gpios = <&gpio1 11  (GPIO_ACTIVE_HIGH|GPIO_PULL_DOWN)>;
 			label = "semtech_sx1262 DIO1";
 		};
 	};
+
+	// Use watchdog wdt31 as the application watchdog
+	watchdog0 = &wdt31;
 };
 
-sid_semtech: &spi21 {
+sid_semtech: &spi30 {
 	compatible = "nordic,nrf-spim";
 	status = "okay";
-	cs-gpios = <&gpio2 0xa GPIO_ACTIVE_LOW>;
-	pinctrl-0 = <&spi21_default>;
-	pinctrl-1 = <&spi21_sleep>;
+	cs-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&spi30_default_alt>;
+	pinctrl-1 = <&spi30_sleep_alt>;
 	pinctrl-names = "default", "sleep";
 	clock-frequency = <DT_FREQ_M(8)>;
 };
 
+// restore full RRAM and SRAM space - by default some parts are dedicated to FLRP
+&cpuapp_rram {
+	reg = <0x0 DT_SIZE_K(1524)>;
+};
+
+&cpuapp_sram {
+	reg = <0x20000000 DT_SIZE_K(256)>;
+	ranges = <0x0 0x20000000  0x40000>;
+};
+
 &pinctrl {
-	spi21_default: spi21_default {
+	spi30_default_alt: spi30_default_alt {
 		group1 {
-			psels = <NRF_PSEL(SPIM_SCK, 2, 6)>,
-			        <NRF_PSEL(SPIM_MISO, 1, 11)>,
-			        <NRF_PSEL(SPIM_MOSI, 2, 8)>;
+			psels = <NRF_PSEL(SPIM_SCK, 0, 3)>,
+				<NRF_PSEL(SPIM_MISO, 0, 2)>,
+				<NRF_PSEL(SPIM_MOSI, 0, 1)>;
 		};
 	};
 
-	spi21_sleep: spi21_sleep {
+	spi30_sleep_alt: spi30_sleep_alt {
 		group1 {
-			psels = <NRF_PSEL(SPIM_SCK, 2, 6)>,
-			        <NRF_PSEL(SPIM_MISO, 1, 11)>,
-			        <NRF_PSEL(SPIM_MOSI, 2, 8)>;
+			psels = <NRF_PSEL(SPIM_SCK, 0, 3)>,
+				<NRF_PSEL(SPIM_MISO, 0, 2)>,
+				<NRF_PSEL(SPIM_MOSI, 0, 1)>;
 			low-power-enable;
 		};
 	};
 };
 
-
 &gpio0 {
 	status = "okay";
 };
@@ -72,6 +87,10 @@ sid_semtech: &spi21 {
 	status = "okay";
 };
 
+&wdt31 {
+	status = "okay";
+};
+
 &mx25r64 {
 	status = "disabled";
 };