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    • RISC-V pipeline processor: A high-performance, open-source CPU design implementing RISC-V architecture with efficient instruction pipeline execution.
      Verilog
      0060Updated Feb 12, 2025Feb 12, 2025
    • Green House Automation
      TypeScript
      1000Updated Feb 12, 2025Feb 12, 2025
    • API Portal of the Department of Computer Engineering https://api.ce.pdn.ac.lk/
      Python
      MIT License
      5180Updated Feb 12, 2025Feb 12, 2025
    • Student and staff profile website of the Department of Computer Engineering, University of Peradeniya https://people.ce.pdn.ac.lk/
      HTML
      176780Updated Feb 12, 2025Feb 12, 2025
    • VR-Multiplayer-Golf-Game allows multiple users to play golf in VR environment. The game features a virtual environment which allows a user to have an immersive experience.
      TypeScript
      1072Updated Feb 12, 2025Feb 12, 2025
    • The RV32IM pipeline processor project designs a 32-bit RISC-V processor with 5 stages: IF, ID, EX, MEM, WB. It supports RV32I base and M-extension (MUL/DIV), using forwarding, stalling, and branch prediction to manage hazards. Implemented in Verilog, it is simulated, tested with RISC-V tools, and optimized for performance.
      Verilog
      1000Updated Feb 12, 2025Feb 12, 2025
    • This is the student project portfolio website of the Department of Computer Engineering, University of Peradeniya. https://projects.ce.pdn.ac.lk
      HTML
      MIT License
      19440Updated Feb 12, 2025Feb 12, 2025
    • This Smart IoT Lighting System is designed for indoor lighting, integrating hardware with cloud connectivity for seamless control. Users can conveniently configure preferences and manage settings via a secure mobile app with voice command support, ensuring personalized and efficient lighting experiences, ease of use, and robust data security.
      TypeScript
      0000Updated Feb 12, 2025Feb 12, 2025
    • Mental health disorders, including panic attacks, are rising globally. Traditional diagnosis relies on self-reports, which can be subjective. Using machine learning and neural networks, our project analyzes physiological and lifestyle data to predict panic attacks, enabling proactive management and intervention to improve mental well-being.
      Jupyter Notebook
      3000Updated Feb 12, 2025Feb 12, 2025
    • JavaScript
      0001Updated Feb 12, 2025Feb 12, 2025
    • This research designs a scalable, NLP-driven intent-based networking architecture for SDNs. It features a three-layered structure: Translation (NLP-based), Policy Optimization (ML/RL-based), and Intent Enforcement (SDN-integrated). The goal is to enhance network management efficiency and adaptability.
      0000Updated Feb 12, 2025Feb 12, 2025
    • Historical Image Restoration using Image In-painting
      Python
      2000Updated Feb 12, 2025Feb 12, 2025
    • TypeScript
      4000Updated Feb 12, 2025Feb 12, 2025
    • An intelligent aquarium system that automates water quality monitoring, fish behaviour and feeding. Key features include pH and temperature measure.
      Dart
      4000Updated Feb 12, 2025Feb 12, 2025
    • The SmartSecure Locker System is an IoT-based solution for secure storage in shared spaces like universities, gyms, and offices. It features real-time locker availability, biometric access, and alternative location suggestions when lockers are full. Users can manage lockers via a mobile app, ensuring convenience and security.
      C++
      3200Updated Feb 12, 2025Feb 12, 2025
    • JavaScript
      0000Updated Feb 12, 2025Feb 12, 2025
    • P-E-BO Desk Companion is an intelligent, interactive robot assistant designed to help with daily tasks and home automation. By integrating IoT, voice recognition, and face recognition, PE-BO adapts to the user's environment, maximizing convenience and interactivity.
      Python
      0000Updated Feb 11, 2025Feb 11, 2025
    • Industrial Workers' Safety Helmet
      JavaScript
      0000Updated Feb 11, 2025Feb 11, 2025
    • This project develops a RISC-V SoC with an integrated Neuromorphic Accelerator for small-scale Spiking Neural Network (SNN) applications. The SoC is designed for low-power, low-latency edge computing, enabling efficient neuromorphic processing for embedded systems and real-time AI workloads.
      Verilog
      0200Updated Feb 11, 2025Feb 11, 2025
    • 0000Updated Feb 10, 2025Feb 10, 2025
    • Smart canteen management system is a system designed to increase the efficiency of cafeterias in different working environments and to provide more user friendly functions such as smart pay, an app to keep track of user activities, digital touch screen for the menu item selection,congestion alert system.
      0050Updated Feb 10, 2025Feb 10, 2025
    • Verilog
      0031Updated Feb 10, 2025Feb 10, 2025
    • This Git repository contains the implementation of a RISC32IM processor pipeline using Verilog. The pipeline includes stages for instruction fetch, decode, execute, memory access, and write-back. The implementation includes a testbench for verification.
      Verilog
      1000Updated Feb 10, 2025Feb 10, 2025
    • TypeScript
      0000Updated Feb 10, 2025Feb 10, 2025
    • This project develops a near-infrared (NIR) device for real-time artery detection and blood flow assessment in microvascular surgeries, especially oral and reconstructive. Featuring a cloud server and a UI, it enhances precision, monitors perfusion, and improves outcomes post-surgery.
      JavaScript
      0000Updated Feb 10, 2025Feb 10, 2025
    • Internal and Public web service provider of the Department of Computer Engineering
      PHP
      MIT License
      133111Updated Feb 10, 2025Feb 10, 2025
    • Github pages website for Department of Computer Engineering, University of Peradeniya. https://cepdnaclk.github.io
      HTML
      28913Updated Feb 9, 2025Feb 9, 2025
    • 0000Updated Feb 8, 2025Feb 8, 2025
    • This repository contains an implementation of a RISC-V RV32IM processor with a 6-stage pipeline architecture. The design includes instruction fetch, decode, execute, memory access, write-back, and an additional stage for improved performance. It supports integer operations, multiplication, and memory access as defined in the RV32IM instruction set.
      Verilog
      0000Updated Feb 7, 2025Feb 7, 2025
    • HTML
      1000Updated Feb 7, 2025Feb 7, 2025