Merge branch 'master' into altera_flow_support

.gitlab-ci.yml

@@ -56,7 +56,7 @@ variables:
   DV_TARGET: cv32a65x
 
 default:
-  tags: [$TAGS_RUNNER]
+  tags: [$TAGS_RUNNER_SIMU]
   artifacts:
     when: always
     paths:
@@ -72,6 +72,7 @@ stages:
 
 .setup_job:
   stage: setup
+  tags: [$TAGS_RUNNER]
   variables:
     GIT_SUBMODULE_STRATEGY: none
   rules: &on_dev
@@ -249,12 +250,6 @@ cvxif-regression:
     DASHBOARD_SORT_INDEX: 5
     DASHBOARD_JOB_CATEGORY: "Basic"
     COLLECT_SIMU_LOGS: 1
-    SPIKE_TANDEM: 1
-  parallel:
-    matrix:
-      - DV_SIMULATORS:
-        - "veri-testharness,spike"
-        - "vcs-testharness"
   script:
     - bash verif/regress/cvxif_verif_regression.sh
     - if [[ $DV_SIMULATORS == *"spike"* ]]; then unset SPIKE_TANDEM; fi # dirty hack to do trace comparison between tandem execution and spike standalone
@@ -263,6 +258,7 @@ cvxif-regression:
 asic-synthesis:
   extends:
     - .synthesis_test
+  tags: [$TAGS_RUNNER_SYNTH]
   variables:
     DASHBOARD_JOB_TITLE: "ASIC Synthesis $DV_TARGET"
     DASHBOARD_JOB_DESCRIPTION: "Synthesis indicator with specific Techno"
@@ -569,7 +565,7 @@ simu-gate:
 fpga-boot:
   extends:
     - .backend_test
-  tags: [fpga,shell]
+  tags: [$TAGS_RUNNER_FPGA]
   needs:
     - build_tools
     - fpga-build
@@ -614,6 +610,7 @@ code_coverage-report:
 
 check gitlab jobs status:
   stage: find failures
+  tags: [$TAGS_RUNNER]
   rules:
     - if: $DASHBOARD_URL && $CI_KIND != "none"
       when: on_failure
@@ -630,6 +627,7 @@ check gitlab jobs status:
 
 merge reports:
   stage: report
+  tags: [$TAGS_RUNNER]
   variables:
     GIT_SUBMODULE_STRATEGY: none
   rules:

.gitlab-ci/expected_synth.yml

@@ -1,2 +1,2 @@
 cv32a65x:
-  gates: 187456
+  gates: 188652

config/gen_from_riscv_config/cv32a65x/isa/isa.adoc

@@ -22,6 +22,7 @@
 |Zbc | RVZbc Carry-less multiplication | Carry-less multiplication is the multiplication in the polynomial ring over GF(2).clmul produces the lower half of the carry-less product and clmulh produces the upper half of the 2✕XLEN carry-less product.clmulr produces bits 2✕XLEN−2:XLEN-1 of the 2✕XLEN carry-less product.
 |Zbs | RVZbs Single bit Instructions | The single-bit instructions provide a mechanism to set, clear, invert, or extract a single bit in a register. The bit is specified by its index.
 |Zicntr | Zicntr | No info found yet for extension Zicntr
+|Zbkb | RVZbkb Bitmanip instructions for Cryptography | The Zbkb extension is a part of the RISC-V Bit-Manipulation (bitmanip) extensions, specifically targeting cryptographic applications. It introduces a set of instructions designed to facilitate operations commonly used in cryptographic algorithms, such as interleaving, packing, and reordering of bits.
 |===
 
 ==== RV32I Base Integer Instructions
@@ -220,4 +221,3 @@
 | BSET | bset rd, rs1, rs2 | X(rd) = X(rs1) \| (1 << (X(rs2) & (XLEN - 1))) | NONE | NONE | This instruction returns rs1 with a single bit set at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2. | Single_bit_Operations 
 | BSETI | bseti rd, rs1, shamt | X(rd) = X(rs1) \| (1 << (shamt & (XLEN - 1))) | NONE | NONE | This instruction returns rs1 with a single bit set at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved. | Single_bit_Operations 
 |===
-

config/gen_from_riscv_config/cv32a65x/isa/isa.rst

@@ -47,6 +47,8 @@ Instructions
 +---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 | Zicntr        | Zicntr_                                             | No info found yet for extension Zicntr                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               |
 +---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| Zbkb          | RVZbkb Bitmanip instructions for Cryptography_      | The Zbkb extension is a part of the RISC-V Bit-Manipulation (bitmanip) extensions, specifically targeting cryptographic applications. It introduces a set of instructions designed to facilitate operations commonly used in cryptographic algorithms, such as interleaving, packing, and reordering of bits.                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        |
++---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 
 RV32I Base Integer Instructions
 -------------------------------
@@ -393,4 +395,3 @@ RVZbs Single bit Instructions
 +--------+----------------------+------------------------------------------------+------------------+--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------+
 | BSETI  | bseti rd, rs1, shamt | X(rd) = X(rs1) | (1 << (shamt & (XLEN - 1)))   | NONE             | NONE               | This instruction returns rs1 with a single bit set at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved.      | Single_bit_Operations |
 +--------+----------------------+------------------------------------------------+------------------+--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------+
-

core/alu.sv

@@ -51,6 +51,9 @@ module alu
   logic lz_tz_empty, lz_tz_wempty;
   logic [CVA6Cfg.XLEN-1:0] orcbw_result, rev8w_result;
 
+  logic [CVA6Cfg.XLEN-1:0] brev8_reversed;
+  logic [            31:0] unzip_gen;
+  logic [            31:0] zip_gen;
   // bit reverse operand_a for left shifts and bit counting
   generate
     genvar k;
@@ -263,6 +266,29 @@ module alu
     end
   end
 
+  // ZKN gen block
+  if (CVA6Cfg.ZKN && CVA6Cfg.RVB) begin : zkn_gen_block
+    genvar i, m, n;
+    // Generate brev8_reversed by reversing bits within each byte
+    for (i = 0; i < (CVA6Cfg.XLEN / 8); i++) begin : brev8_gen
+      for (m = 0; m < 8; m++) begin : reverse_bits
+        // Reversing the order of bits within a single byte
+        assign brev8_reversed[(i<<3)+m] = fu_data_i.operand_a[(i<<3)+(7-m)];
+      end
+    end
+    // Generate zip and unzip results
+    if (CVA6Cfg.IS_XLEN32) begin
+      for (n = 0; n < 16; n++) begin : zip_unzip_gen
+        // Assigning lower and upper half of operand into the even and odd positions of result
+        assign zip_gen[n<<1] = fu_data_i.operand_a[n];
+        assign zip_gen[(n<<1)+1] = fu_data_i.operand_a[n+16];
+        // Assigning even and odd bits of operand into lower and upper halves of result
+        assign unzip_gen[n] = fu_data_i.operand_a[n<<1];
+        assign unzip_gen[n+16] = fu_data_i.operand_a[(n<<1)+1];
+      end
+    end
+  end
+
   // -----------
   // Result MUX
   // -----------
@@ -358,5 +384,22 @@ module alu
         default: ;  // default case to suppress unique warning
       endcase
     end
+    // ZKN instructions
+    if (CVA6Cfg.ZKN && CVA6Cfg.RVB) begin
+      unique case (fu_data_i.operation)
+        PACK:
+        result_o = (CVA6Cfg.IS_XLEN32) ? ({fu_data_i.operand_b[15:0], fu_data_i.operand_a[15:0]}) : ({fu_data_i.operand_b[31:0], fu_data_i.operand_a[31:0]});
+        PACK_H:
+        result_o = (CVA6Cfg.IS_XLEN32) ? ({16'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]}) : ({48'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]});
+        BREV8: result_o = brev8_reversed;
+        default: ;
+      endcase
+      if (fu_data_i.operation == PACK_W && CVA6Cfg.IS_XLEN64)
+        result_o = {
+          {32{fu_data_i.operand_b[15]}}, {fu_data_i.operand_b[15:0]}, {fu_data_i.operand_a[15:0]}
+        };
+      if (fu_data_i.operation == UNZIP && CVA6Cfg.IS_XLEN32) result_o = unzip_gen;
+      if (fu_data_i.operation == ZIP && CVA6Cfg.IS_XLEN32) result_o = zip_gen;
+    end
   end
 endmodule

core/csr_regfile.sv

@@ -35,7 +35,7 @@ module csr_regfile
     // halt requested - CONTROLLER
     output logic halt_csr_o,
     // Instruction to be committed - ID_STAGE
-    input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i,
+    input scoreboard_entry_t commit_instr_i,
     // Commit acknowledged a instruction -> increase instret CSR - COMMIT_STAGE
     input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i,
     // Address from which to start booting, mtvec is set to the same address - SUBSYSTEM
@@ -2000,11 +2000,11 @@ module csr_regfile
         dcsr_d.prv = priv_lvl_o;
         dcsr_d.v   = (!CVA6Cfg.RVH) ? 1'b0 : v_q;
         // valid CTRL flow change
-        if (commit_instr_i[0].fu == CTRL_FLOW) begin
+        if (commit_instr_i.fu == CTRL_FLOW) begin
           // we saved the correct target address during execute
           dpc_d = {
-            {CVA6Cfg.XLEN - CVA6Cfg.VLEN{commit_instr_i[0].bp.predict_address[CVA6Cfg.VLEN-1]}},
-            commit_instr_i[0].bp.predict_address
+            {CVA6Cfg.XLEN - CVA6Cfg.VLEN{commit_instr_i.bp.predict_address[CVA6Cfg.VLEN-1]}},
+            commit_instr_i.bp.predict_address
           };
           // exception valid
         end else if (ex_i.valid) begin
@@ -2015,8 +2015,8 @@ module csr_regfile
           // consecutive PC
         end else begin
           dpc_d = {
-            {CVA6Cfg.XLEN - CVA6Cfg.VLEN{commit_instr_i[0].pc[CVA6Cfg.VLEN-1]}},
-            commit_instr_i[0].pc + (commit_instr_i[0].is_compressed ? 'h2 : 'h4)
+            {CVA6Cfg.XLEN - CVA6Cfg.VLEN{commit_instr_i.pc[CVA6Cfg.VLEN-1]}},
+            commit_instr_i.pc + (commit_instr_i.is_compressed ? 'h2 : 'h4)
           };
         end
         debug_mode_d   = 1'b1;

core/cva6.sv

@@ -1088,7 +1088,7 @@ module cva6
       .time_irq_i,
       .flush_o                 (flush_csr_ctrl),
       .halt_csr_o              (halt_csr_ctrl),
-      .commit_instr_i          (commit_instr_id_commit),
+      .commit_instr_i          (commit_instr_id_commit[0]),
       .commit_ack_i            (commit_ack),
       .boot_addr_i             (boot_addr_i[CVA6Cfg.VLEN-1:0]),
       .hart_id_i               (hart_id_i[CVA6Cfg.XLEN-1:0]),

core/cva6_rvfi.sv

@@ -284,8 +284,8 @@ module cva6_rvfi
                   ex_commit_cause == riscv::ENV_CALL_UMODE));
       rvfi_instr_o[i].valid <= valid;
       rvfi_instr_o[i].insn  <= mem_q[commit_pointer[i]].instr;
-      // when trap, the instruction is not executed
-      rvfi_instr_o[i].trap  <= exception;
+      // when synchronous trap, the instruction is not executed
+      rvfi_instr_o[i].trap  <= exception && !ex_commit_cause[31];
 
       if (exception && ex_commit_cause[31]) begin
         rvfi_intr[i] <= 'b101;

core/cvxif_compressed_if_driver.sv

@@ -21,13 +21,14 @@ module cvxif_compressed_if_driver #(
 
     input logic [CVA6Cfg.NrIssuePorts-1:0]       is_compressed_i,
     input logic [CVA6Cfg.NrIssuePorts-1:0]       is_illegal_i,
+    input logic [CVA6Cfg.NrIssuePorts-1:0]       instruction_valid_i,
     input logic [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction_i,
 
     output logic               [CVA6Cfg.NrIssuePorts-1:0]       is_compressed_o,
     output logic               [CVA6Cfg.NrIssuePorts-1:0]       is_illegal_o,
     output logic               [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction_o,
     input  logic                                                stall_i,
-    output logic                                                stall_o,
+    output logic               [CVA6Cfg.NrIssuePorts-1:0]       stall_o,
     // CVXIF Compressed interface
     input  logic                                                compressed_ready_i,
     input  x_compressed_resp_t                                  compressed_resp_i,
@@ -43,30 +44,31 @@ module cvxif_compressed_if_driver #(
     compressed_valid_o      = 1'b0;
     compressed_req_o.instr  = '0;
     compressed_req_o.hartid = hart_id_i;
-    stall_o                 = stall_i;
+    stall_o[0]              = stall_i;
+    stall_o[1]              = 1'b0;
     if (is_illegal_i[0]) begin
-      compressed_valid_o = is_illegal_i[0];
+      compressed_valid_o = is_illegal_i[0] && instruction_valid_i[0];
       compressed_req_o.instr = instruction_i[0][15:0];
       is_illegal_o[0] = ~compressed_resp_i.accept;
       instruction_o[0] = compressed_resp_i.accept ? compressed_resp_i.instr : instruction_i[0];
       is_compressed_o[0] = compressed_resp_i.accept ? 1'b0 : is_compressed_i[0];
       if (~stall_i) begin
         // Propagate stall from macro decoder or wait for compressed ready if compressed transaction is happening.
         // Stall if both instruction are illegal
+        stall_o[0] = (compressed_valid_o && ~compressed_ready_i);
         if (CVA6Cfg.SuperscalarEn) begin
-          stall_o = is_illegal_i[1];
-        end else begin
-          stall_o = (compressed_valid_o && ~compressed_ready_i);
+          stall_o[1] = is_illegal_i[1];
         end
       end
     end
     if (CVA6Cfg.SuperscalarEn) begin
       if (~is_illegal_i[0] && is_illegal_i[1]) begin  // 2nd instruction is illegal
-        compressed_valid_o = is_illegal_i[1];
+        compressed_valid_o = is_illegal_i[1] && instruction_valid_i[1];
         compressed_req_o.instr = instruction_i[1][15:0];
         is_illegal_o[1] = ~compressed_resp_i.accept;
         instruction_o[1] = compressed_resp_i.accept ? compressed_resp_i.instr : instruction_i[1];
         is_compressed_o[1] = compressed_resp_i.accept ? 1'b0 : is_compressed_i[1];
+        stall_o[1] = (compressed_valid_o && ~compressed_ready_i);
       end
     end
   end

core/cvxif_issue_register_commit_if_driver.sv

@@ -60,7 +60,7 @@ module cvxif_issue_register_commit_if_driver #(
 
   // Always do commit transaction with issue
   // If instruction goes to execute then it is not speculative
-  assign commit_valid_o       = issue_valid_o;
+  assign commit_valid_o       = issue_valid_o && issue_ready_i;
   assign commit_o.hartid      = issue_req_o.hartid;
   assign commit_o.id          = issue_req_o.id;
   assign commit_o.commit_kill = 1'b0;