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Original file line number | Diff line number | Diff line change |
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@@ -1,7 +1,7 @@ | ||
# -*- coding: utf-8 -*- | ||
# Copyright 2014-present PlatformIO <[email protected]> | ||
# Copyright 2016 Juan González <[email protected]> | ||
# Jesús Arroyo Torrens <[email protected]> | ||
# Copyright 2016-present Juan González <[email protected]> | ||
# Jesús Arroyo Torrens <[email protected]> | ||
# | ||
# Licensed under the Apache License, Version 2.0 (the "License"); | ||
# you may not use this file except in compliance with the License. | ||
|
@@ -16,7 +16,7 @@ | |
# limitations under the License. | ||
|
||
""" | ||
Build script for lattice ice40 FPGAs | ||
Build script for Lattice iCE40 FPGAs | ||
""" | ||
|
||
import os | ||
|
@@ -28,8 +28,12 @@ | |
Glob) | ||
|
||
env = DefaultEnvironment() | ||
env.Replace(PROGNAME="hardware") | ||
env.Append(SIMULNAME="simulation") | ||
env.Replace( | ||
PROGNAME='hardware', | ||
UPLOADER='iceprog', | ||
UPLOADERFLAGS=[], | ||
UPLOADBINCMD='$UPLOADER $UPLOADERFLAGS $SOURCES') | ||
env.Append(SIMULNAME='simulation') | ||
|
||
# -- Target name for synthesis | ||
TARGET = join(env['BUILD_DIR'], env['PROGNAME']) | ||
|
@@ -39,11 +43,18 @@ | |
IVL_PATH = join( | ||
pioPlatform.get_package_dir('toolchain-iverilog'), 'lib', 'ivl') | ||
VLIB_PATH = join( | ||
pioPlatform.get_package_dir('toolchain-iverilog'), 'vlib', 'system.v') | ||
pioPlatform.get_package_dir('toolchain-iverilog'), 'vlib') | ||
VLIB_FILES = ' '.join([ | ||
'"{}"'.format(f) for f in Glob(join(VLIB_PATH, '*.v')) | ||
]) if VLIB_PATH else '' | ||
|
||
isWindows = 'Windows' != system() | ||
VVP_PATH = '-M {0}'.format(IVL_PATH) if isWindows else '' | ||
IVER_PATH = '-B {0}'.format(IVL_PATH) if isWindows else '' | ||
CHIPDB_PATH = join( | ||
pioPlatform.get_package_dir('toolchain-icestorm'), 'share', 'icebox', | ||
'chipdb-{0}.txt'.format(env.BoardConfig().get('build.size', '1k'))) | ||
|
||
isWindows = 'Windows' == system() | ||
VVP_PATH = '' if isWindows else '-M "{0}"'.format(IVL_PATH) | ||
IVER_PATH = '' if isWindows else '-B "{0}"'.format(IVL_PATH) | ||
|
||
# -- Get a list of all the verilog files in the src folfer, in ASCII, with | ||
# -- the full path. All these files are used for the simulation | ||
|
@@ -53,10 +64,10 @@ | |
# --- Get the Testbench file (there should be only 1) | ||
# -- Create a list with all the files finished in _tb.v. It should contain | ||
# -- the test bench | ||
list_tb = [f for f in src_sim if f[-5:].upper() == "_TB.V"] | ||
list_tb = [f for f in src_sim if f[-5:].upper() == '_TB.V'] | ||
|
||
if len(list_tb) > 1: | ||
print "---> WARNING: More than one testbenches used" | ||
print('---> WARNING: More than one testbenches used') | ||
|
||
# -- Error checking | ||
try: | ||
|
@@ -66,46 +77,54 @@ | |
except IndexError: | ||
testbench = None | ||
|
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if 'sim' in COMMAND_LINE_TARGETS: | ||
SIMULNAME = '' | ||
TARGET_SIM = '' | ||
|
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# clean | ||
if len(COMMAND_LINE_TARGETS) == 0: | ||
if testbench is not None: | ||
# -- Simulation name | ||
testbench_file = os.path.split(testbench)[-1] | ||
SIMULNAME, ext = os.path.splitext(testbench_file) | ||
# sim | ||
elif 'sim' in COMMAND_LINE_TARGETS: | ||
if testbench is None: | ||
print "---> ERROR: NO testbench found for simulation" | ||
print('---> ERROR: NO testbench found for simulation') | ||
Exit(1) | ||
|
||
# -- Simulation name | ||
testbench_file = os.path.split(testbench)[-1] | ||
SIMULNAME, ext = os.path.splitext(testbench_file) | ||
else: | ||
SIMULNAME = '' | ||
|
||
TARGET_SIM = join(env.subst('$BUILD_DIR'), SIMULNAME) | ||
# -- Target sim name | ||
if SIMULNAME: | ||
TARGET_SIM = join(env.subst('$BUILD_DIR'), SIMULNAME).replace('\\', '\\\\') | ||
|
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# --- Get the synthesis files. They are ALL the files except the testbench | ||
src_synth = [f for f in src_sim if f not in list_tb] | ||
|
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# -- For debugging | ||
print "Testbench: %s" % testbench | ||
|
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# -- Get the PCF file | ||
src_dir = env.subst('$PROJECTSRC_DIR') | ||
PCFs = join(src_dir, '*.pcf') | ||
PCF_list = Glob(PCFs) | ||
PCF = '' | ||
|
||
try: | ||
PCF = PCF_list[0] | ||
except IndexError: | ||
print "---> ERROR: no .pcf file found" | ||
Exit(1) | ||
print('---> WARNING: no .pcf file found') | ||
|
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# -- Debug | ||
print "PCF: %s" % PCF | ||
|
||
# -- Builder 1 (.v --> .blif) | ||
# | ||
# Builder: Yosys (.v --> .blif) | ||
# | ||
synth = Builder( | ||
action='yosys -p \"synth_ice40 -blif $TARGET\" $SOURCES', | ||
action='yosys -p \"synth_ice40 -blif $TARGET\" -q $SOURCES', | ||
suffix='.blif', | ||
src_suffix='.v') | ||
|
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# -- Builder 2 (.blif --> .asc) | ||
# | ||
# Builder: Arachne-pnr (.blif --> .asc) | ||
# | ||
pnr = Builder( | ||
action='arachne-pnr -d {0} -P {1} -p {2} -o $TARGET $SOURCE'.format( | ||
env.BoardConfig().get('build.size', '1k'), | ||
|
@@ -115,73 +134,91 @@ | |
suffix='.asc', | ||
src_suffix='.blif') | ||
|
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# -- Builder 3 (.asc --> .bin) | ||
# | ||
# Builder: Icepack (.asc --> .bin) | ||
# | ||
bitstream = Builder( | ||
action='icepack $SOURCE $TARGET', | ||
suffix='.bin', | ||
src_suffix='.asc') | ||
|
||
# -- Builder 4 (.asc --> .rpt) | ||
# NOTE: new icetime requires a fixed PREFIX during compilation | ||
# update on toolchain-icestorm 1.10.0 | ||
# https://github.com/cliffordwolf/icestorm/issues/57 | ||
# | ||
# Builder: Icetime (.asc --> .rpt) | ||
# | ||
time_rpt = Builder( | ||
action='icetime -d {0}{1} -P {2} -mtr $TARGET $SOURCE'.format( | ||
action='icetime -d {0}{1} -P {2} -C "{3}" -mtr $TARGET $SOURCE'.format( | ||
env.BoardConfig().get('build.type', 'hx'), | ||
env.BoardConfig().get('build.size', '1k'), | ||
env.BoardConfig().get('build.pack', 'tq144') | ||
env.BoardConfig().get('build.pack', 'tq144'), | ||
CHIPDB_PATH | ||
), | ||
suffix='.rpt', | ||
src_suffix='.asc') | ||
|
||
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env.Append(BUILDERS={ | ||
'Synth': synth, 'PnR': pnr, 'Bin': bitstream, 'Time': time_rpt}) | ||
|
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blif = env.Synth(TARGET, [src_synth]) | ||
asc = env.PnR(TARGET, [blif, PCF]) | ||
binf = env.Bin(TARGET, asc) | ||
|
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upload = env.Alias('upload', binf, 'iceprog $SOURCE') | ||
AlwaysBuild(upload) | ||
|
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# -- Target for calculating the time (.rpt) | ||
# | ||
# Target: Time analysis (.rpt) | ||
# | ||
rpt = env.Time(asc) | ||
t = env.Alias('time', rpt) | ||
AlwaysBuild(t) | ||
|
||
# -- Icarus Verilog builders | ||
iverilog = Builder( | ||
action='iverilog {0} -o $TARGET {1} -D VCD_OUTPUT={2} $SOURCES'.format( | ||
IVER_PATH, VLIB_PATH, TARGET_SIM), | ||
suffix='.out', | ||
src_suffix='.v') | ||
target_time = env.Alias('time', rpt) | ||
AlwaysBuild(target_time) | ||
|
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# | ||
# Target: Upload bitstream | ||
# | ||
target_upload = env.Alias('upload', binf, '$UPLOADBINCMD') | ||
AlwaysBuild(target_upload) | ||
|
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# NOTE: output file name is defined in the iverilog call using VCD_OUTPUT macro | ||
# | ||
# Builders: Icarus Verilog | ||
# | ||
iverilog = Builder( | ||
action='iverilog {0} -o $TARGET -D VCD_OUTPUT={1} {2} $SOURCES'.format( | ||
IVER_PATH, TARGET_SIM, VLIB_FILES), | ||
suffix='.out', | ||
src_suffix='.v') | ||
vcd = Builder( | ||
action='vvp {0} $SOURCE'.format( | ||
VVP_PATH), | ||
suffix='.vcd', | ||
src_suffix='.out') | ||
# NOTE: output file name is defined in the | ||
# iverilog call using VCD_OUTPUT macro | ||
|
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env.Append(BUILDERS={'IVerilog': iverilog, 'VCD': vcd}) | ||
|
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# --- Verify | ||
# | ||
# Target: Verify verilog code | ||
# | ||
vout = env.IVerilog(TARGET, src_synth) | ||
|
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verify = env.Alias('verify', vout) | ||
AlwaysBuild(verify) | ||
target_verify = env.Alias('verify', vout) | ||
AlwaysBuild(target_verify) | ||
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# --- Simulation | ||
# | ||
# Target: Simulate testbench | ||
# | ||
sout = env.IVerilog(TARGET_SIM, src_sim) | ||
vcd_file = env.VCD(sout) | ||
|
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waves = env.Alias('sim', vcd_file, 'gtkwave {0} {1}.gtkw'.format( | ||
target_sim = env.Alias('sim', vcd_file, 'gtkwave {0} {1}.gtkw'.format( | ||
vcd_file[0], join(env['PROJECTSRC_DIR'], SIMULNAME))) | ||
AlwaysBuild(waves) | ||
AlwaysBuild(target_sim) | ||
|
||
# | ||
# Setup default targets | ||
# | ||
Default([binf]) | ||
|
||
# -- These is for cleaning the files generated using the alias targets | ||
# | ||
# Target: Clean generated files | ||
# | ||
if GetOption('clean'): | ||
env.Default([t, vout, sout, vcd_file]) |
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