More explicit ro, rw, rw1c, etc in state machine semantics

[samuelgruetter]

The opentitan docs (eg the HMAC module docs) mention for each bit of each register a so-called "Type" (also called "swaccess key"), which must be one of the following values (copied from the register tool doc):

Key	Description
none	No access
ro	Read Only
rc	Read Only, reading clears
rw	Read/Write
r0w1c	Read zero, Write with 1 clears
rw1s	Read, Write with 1 sets
rw1c	Read, Write with 1 clears
rw0c	Read, Write with 0 clears
wo	Write Only

In our current state machine semantics, this implicitly follows from which kind of transitions our state machines allow. It might be good to make this more explicit, so that it matches the English specs more closely, but I don't quite know how.