Nano-Processor-Design

All VHDL files are in relevant folders and there are included screenshots of simulations for each component
The final files are inside Lab-9-10.srcs

http://dilum.bandara.lk/wp-content/uploads/CourseNotes/CS2052CA/Lab-9-10-–-Nanoprocessor-Design-Competition.pdf

Mulitplexers

2-way 3-bit Mulitplexer - DONE ✅

Note:
When Selector is 0 Line0 will be passed and Selector is 1, Line 1 will be passed. Edit: Changed the code to use logic gates.

2-way 4-bit Mulitplexer - DONE ✅

Note:
Similar to 2 way 3 bit multiplexer.

8 way 4-bit Multiplexer - DONE ✅

Note:
Used logic gates to build.

Program ROM - DONE ✅

Note:
Simple Lookup table, uses 13-bit instructions so we can include some more additional instructions if we need.

3-Bit Adder - DONE ✅

Note:
Adder only has one input, other input is always 1 Once '111' is reached the output will reset to '000' and C_out will become '1', which could be useful to indicate an end of program instructions.

Program Counter - DONE ✅

Note:
Program Counter has an input and a output. While output will only be set when the clock edge is 'falling'. Had to use D-Flip flops from Lab5.

4-bit Adder-Sub Unit - DONE ✅

Note:
OverFlow and ZeroFlag are the main differences. Also input B is the input which will be converted to its negative when we try to subtract the 2 numbers by setting M = '1'.

Register Bank - DONE ✅

Note:
We included 8 registers with a 3 to 8 decoder to select which register to enable. Also Register 0 is hardcoded to "0000" so it doesn't interfere with the adder when we want to select only one register.

Instruction Decoder - DONE ✅

Note:
INCLUDE THE LOGIC FOR 13th BIT!!!!! All instructions were tested and simulated. I have created a 13 bit instruction, so we can include extra instructions in the future as need be. Also we could use the zero flag from the 4bit adder to directly for the Jump instruction.