[ARM64_DYNAREC] Added weakbarrier=2 to disable last write barriers (#…

…2049)
ptitSeb · Nov 19, 2024 · fa432bb · fa432bb
1 parent 81e4e26
commit fa432bb
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Showing 5 changed files with 19 additions and 17 deletions.
diff --git a/docs/USAGE.md b/docs/USAGE.md
@@ -177,6 +177,7 @@ Enable/Disable simulation of Strong Memory model
 Use weak memory barriers to reduce the performance impact by STRONGMEM
 * 0 : Use regular safe barrier (Default.)
 * 1 : Use weak barriers to have more performance boost
+* 2 : Disable the last write barriers to have even more performance boost
 
 #### BOX64_DYNAREC_X87DOUBLE *
 Force the use of Double for x87 emulation

diff --git a/docs/box64.pod b/docs/box64.pod
@@ -306,6 +306,7 @@ Use weak memory barriers to reduce the performance impact by STRONGMEM
 
     * 0 : Use regular safe barrier (Default.)
     * 1 : Use weak barriers to have more performance boost
+    * 2 : Disable the last write barriers to have even more performance boost
 
 =item B<BOX64_DYNAREC_X87DOUBLE>=I<0|1>
 

diff --git a/src/core.c b/src/core.c
@@ -789,7 +789,7 @@ void LoadLogEnv()
     p = getenv("BOX64_DYNAREC_WEAKBARRIER");
     if (p) {
         if (strlen(p) == 1) {
-            if (p[0] >= '0' && p[0] <= '1')
+            if (p[0] >= '0' && p[0] <= '2')
                 box64_dynarec_weakbarrier = p[0] - '0';
         }
         if (box64_dynarec_weakbarrier)

diff --git a/src/dynarec/arm64/dynarec_arm64_helper.h b/src/dynarec/arm64/dynarec_arm64_helper.h
@@ -161,21 +161,21 @@
     } while (0)
 
 // An opcode will write memory, this will be put before the STORE instruction automatically.
-#define WILLWRITE()                                                                                   \
-    do {                                                                                              \
-        if (box64_dynarec_strongmem >= dyn->insts[ninst].will_write && dyn->smwrite == 0) {           \
-            /* Will write but never written, this is the start of a SEQ, put a barrier. */            \
-            if (box64_dynarec_weakbarrier)                                                            \
-                DMB_ISHST();                                                                          \
-            else                                                                                      \
-                DMB_ISH();                                                                            \
-        } else if (box64_dynarec_strongmem >= STRONGMEM_LAST_WRITE && dyn->insts[ninst].last_write) { \
-            /* Last write, put a barrier */                                                           \
-            if (box64_dynarec_weakbarrier)                                                            \
-                DMB_ISHST();                                                                          \
-            else                                                                                      \
-                DMB_ISH();                                                                            \
-        }                                                                                             \
+#define WILLWRITE()                                                                                                                     \
+    do {                                                                                                                                \
+        if (box64_dynarec_strongmem >= dyn->insts[ninst].will_write && dyn->smwrite == 0) {                                             \
+            /* Will write but never written, this is the start of a SEQ, put a barrier. */                                              \
+            if (box64_dynarec_weakbarrier)                                                                                              \
+                DMB_ISHST();                                                                                                            \
+            else                                                                                                                        \
+                DMB_ISH();                                                                                                              \
+        } else if (box64_dynarec_strongmem >= STRONGMEM_LAST_WRITE && box64_dynarec_weakbarrier <= 1 && dyn->insts[ninst].last_write) { \
+            /* Last write, put a barrier */                                                                                             \
+            if (box64_dynarec_weakbarrier)                                                                                              \
+                DMB_ISHST();                                                                                                            \
+            else                                                                                                                        \
+                DMB_ISH();                                                                                                              \
+        }                                                                                                                               \
     } while (0)
 
 // Similar to WILLWRITE, but checks lock.

diff --git a/src/tools/rcfile.c b/src/tools/rcfile.c
@@ -156,7 +156,7 @@ ENTRYINT(BOX64_DYNAREC_LOG, box64_dynarec_log, 0, 3, 2)             \
 ENTRYINT(BOX64_DYNAREC_BIGBLOCK, box64_dynarec_bigblock, 0, 3, 2)   \
 ENTRYSTRING_(BOX64_DYNAREC_FORWARD, box64_dynarec_forward)          \
 ENTRYINT(BOX64_DYNAREC_STRONGMEM, box64_dynarec_strongmem, 0, 4, 3) \
-ENTRYBOOL(BOX64_DYNAREC_WEAKBARRIER, box64_dynarec_weakbarrier)     \
+ENTRYINT(BOX64_DYNAREC_WEAKBARRIER, box64_dynarec_weakbarrier, 0, 2, 2) \
 ENTRYBOOL(BOX64_DYNAREC_X87DOUBLE, box64_dynarec_x87double)         \
 ENTRYBOOL(BOX64_DYNAREC_DIV0, box64_dynarec_div0)                   \
 ENTRYBOOL(BOX64_DYNAREC_FASTNAN, box64_dynarec_fastnan)             \