Add implementation flow for VCU118.

.gitignore

@@ -11,6 +11,15 @@ spatz
 # Documentation site
 site/
 
+# Xilinx flow generated
+target/xilinx/*/.Xil
+target/xilinx/*/scripts/add_sources.tcl*
+target/xilinx/*/scripts/add_includes.tcl
+target/xilinx/*/out/
+probes.ltx
+target/xilinx/*/carfield_vcu128/
+target/xilinx/*/carfield_vcu118/
+
 # sw auto-generated
 sw/tests/bare-metal/safed/*.h
 sw/tests/bare-metal/pulpd/*.h

Bender.local

@@ -4,7 +4,7 @@
 
 overrides:
   axi:                  { git: https://github.com/pulp-platform/axi.git                   , version: 0.39.3 }
-  axi_riscv_atomics:    { git: https://github.com/pulp-platform/axi_riscv_atomics.git     , rev: 46d567cad5a614a82778702d48b3a789aed7711b } # branch: astral
+  axi_riscv_atomics:    { git: https://github.com/pulp-platform/axi_riscv_atomics.git     , rev: 062bc36cbcca25629384e7f12efa6693273b3e07 } # branch: astral
   apb:                  { git: "https://github.com/pulp-platform/apb.git"                 , version: 0.2.3 }
   redundancy_cells:     { git: "https://github.com/pulp-platform/redundancy_cells.git"    , rev: "c37bdb47339bf70e8323de8df14ea8bbeafb6583" } # branch: astral-rebase
   hci:                  { git: "https://github.com/pulp-platform/hci.git"                 , rev: d31af36ebcaf2196fb51676b40782aa8cbd9cc69   } # branch: remove-automatic-parameter-prop

Bender.lock

@@ -66,7 +66,7 @@ packages:
     - common_cells
     - obi
   axi_riscv_atomics:
-    revision: 46d567cad5a614a82778702d48b3a789aed7711b
+    revision: 062bc36cbcca25629384e7f12efa6693273b3e07
     version: null
     source:
       Git: https://github.com/pulp-platform/axi_riscv_atomics.git
@@ -202,7 +202,7 @@ packages:
     - fpnew
     - tech_cells_generic
   dyn_mem:
-    revision: 480590062742230dc9bd4050358a15b4747bdf34
+    revision: 6753d2046da6dfc8efbef5e6f22053a621f111d9
     version: null
     source:
       Git: https://github.com/pulp-platform/dyn_spm.git

Bender.yml

@@ -15,7 +15,7 @@ dependencies:
   axi:                { git: https://github.com/pulp-platform/axi.git,                  version: 0.39.1                               }
   cheshire:           { git: https://github.com/pulp-platform/cheshire.git,             rev: d6274a52dab68d12765b64d670d528774eb36c2c } # branch: idma-rebase
   hyperbus:           { git: https://github.com/pulp-platform/hyperbus.git,             rev: f039e601c8b6590181734e6d26ff8b77aa380412 } # branch: chi/add_fsm_with_Tcsh
-  dyn_mem:            { git: https://github.com/pulp-platform/dyn_spm.git,              rev: 480590062742230dc9bd4050358a15b4747bdf34 } # branch: main
+  dyn_mem:            { git: https://github.com/pulp-platform/dyn_spm.git,              rev: 6753d2046da6dfc8efbef5e6f22053a621f111d9 } # branch: astral
   safety_island:      { git: https://github.com/pulp-platform/safety_island.git,        rev: aaef55c798ab53560faaf451a86668fa1e6d0f3b } # branch: carfield
   pulp_cluster:       { git: https://github.com/pulp-platform/pulp_cluster.git,         rev: 1a167ec4ec46fa4a0c3d054b1213c0e6bc15d075 } # branch: astral
   opentitan:          { git: https://github.com/pulp-platform/opentitan.git,            rev: faca6f28e20195e9b56eb822c58bec4a3a19dd4f } # branch: mc/astral
@@ -99,7 +99,7 @@ sources:
     files:
       - hw/spatz_cluster_wrapper.sv
 
-  - target: test
+  - target: all(test, not(fpga))
     files:
       - target/sim/src/hyp_vip/s27ks0641.v
       - target/sim/src/vip_carfield_soc.sv

bender-xilinx.mk

@@ -6,6 +6,7 @@
 
 # bender targets
 xilinx_targs_common += -t fpga
+xilinx_targs_common += -t xilinx
 
 # bender defines
 xilinx_defs_common += -D PULP_FPGA_EMUL

carfield.mk

@@ -47,7 +47,7 @@ include $(CAR_ROOT)/bender-safed.mk
 ######################
 
 CAR_NONFREE_REMOTE ?= [email protected]:astral/astral-nonfree.git
-CAR_NONFREE_COMMIT ?= e8e4354d084cf1cfe6eb9b3bae6af381ef9108b1 # branch: master
+CAR_NONFREE_COMMIT ?= 616e11ac35e68477cf96cad5cd2297123911a28d # branch: vcu-118
 
 ## @section Carfield platform nonfree components
 ## Clone the non-free verification IP for Carfield. Some components such as CI scripts and ASIC

sw/boot/carfield.dtsi

@@ -13,150 +13,7 @@
   chosen {
     stdout-path = "/soc/serial@3002000:38400";
   };
-  memory@80000000 {
-    device_type = "memory";
-    reg = <0x0 0x80000000 0x0 0x40000000>;
-  };
-  cpus {
-    #address-cells = <1>;
-    #size-cells = <0>;
-    timebase-frequency = <1000000>; // 1 MHz
-    CPU0: cpu@0 {
-      device_type = "cpu";
-      status = "okay";
-      compatible = "eth,ariane", "riscv";
-      clock-frequency = <50000000>; // 50 MHz
-      riscv,isa = "rv64imafdc";
-      mmu-type = "riscv,sv39";
-      tlb-split;
-      reg = <0>;
-      CPU0_intc: interrupt-controller {
-        #address-cells = <0>;
-        #interrupt-cells = <1>;
-        interrupt-controller;
-        compatible = "riscv,cpu-intc";
-      };
-    };
-  };
-  sysclk: virt_50mhz {
-    #clock-cells = <0>;
-    compatible = "fixed-clock";
-    clock-frequency = <50000000>;
-  };
-  soc: soc {
-    #address-cells = <2>;
-    #size-cells = <2>;
-    compatible = "eth,carfield-soc", "eth,cheshire-bare-soc", "simple-bus";
-    ranges;
-    debug@0 {
-      compatible = "riscv,debug-013";
-      reg-names = "control";
-      reg = <0x0 0x0 0x0 0x1000>;
-    };
-    ctrl-regs@3000000 {
-      compatible = "eth,control-regs";
-      reg = <0x0 0x3000000 0x0 0x1000>;
-    };
-    axi_llc@3001000 {
-      compatible = "eth,axi-llc";
-      reg = <0x0 0x3001000 0x0 0x5000>;
-    };
-    ddr_link: memory-controller@3006000 {
-      compatible = "eth,ddr-link";
-      reg = <0x0 0x3006000 0x0 0x1000>;
-    };
-    serial@3002000 {
-      compatible = "ns16550a";
-      clock-frequency = <50000000>; // 50 MHz
-      current-speed = <38400>;
-      interrupt-parent = <&PLIC0>;
-      interrupts = <1>;
-      reg = <0x0 0x3002000 0x0 0x1000>;
-      reg-shift = <2>; // regs are spaced on 32 bit boundary
-      reg-io-width = <4>; // only 32-bit access are supported
-    };
-    spi@3004000 {
-      compatible = "opentitan,spi-host", "lowrisc,spi";
-      interrupt-parent = <&PLIC0>;
-      interrupts = <17 18>;
-      reg = <0x0 0x3004000 0x0 0x1000>;
-      clock-frequency = <50000000>;
-      max-frequency = <20000000>;
-      #address-cells = <1>;
-      #size-cells = <0>;
-      boot-with = <1>;
-      nor@1 {
-        #address-cells = <0x1>;
-        #size-cells = <0x1>;
-        // Note : u-boot does not find mt25qu02g
-        compatible = "mt25qu02g", "jedec,spi-nor";
-        reg = <0x1>; // CS
-        spi-max-frequency = <20000000>;
-        spi-rx-bus-width = <0x1>;
-        spi-tx-bus-width = <0x1>;
-        disable-wp;
-        partition@0 {
-          label = "all";
-          reg = <0x0 0x6000000>; // 96 MB
-          read-only;
-        };
-      };
-    };
-    clint@2040000 {
-      compatible = "riscv,clint0";
-      interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7>;
-      reg-names = "control";
-      reg = <0x0 0x2040000 0x0 0x040000>;
-    };
-    PLIC0: interrupt-controller@4000000 {
-      compatible = "riscv,plic0";
-      #address-cells = <0>;
-      #interrupt-cells = <1>;
-      interrupt-controller;
-      interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
-      riscv,max-priority = <7>;
-      riscv,ndev = <51>;
-      reg = <0x0 0x4000000 0x0 0x4000000>;
-    };
-    gpio@3005000 {
-      compatible = "gpio,carfield";
-      reg = <0x0 0x3005000 0x0 0x1000>;
-      interrupts-extended = <&PLIC0 19 &PLIC0 21 &PLIC0 22 &PLIC0 24>;
-    };
-    tcdm@10000000 {
-      reg = <0x0 0x10000000 0x0 0x400000>;
-    };
-    soc-ctrl@20010000 {
-      compatible = "soc-ctrl,carfield";
-      reg = <0x0 0x20010000 0x0 0x1000>;
-    };
-    l2-intl-0@78000000 {
-      compatible = "l2-intl,carfield";
-      reg = <0x0 0x78000000 0x0 0x100000>;
-    };
-    l2-cont-0@78100000 {
-      compatible = "l2-cont,carfield";
-      reg = <0x0 0x78100000 0x0 0x100000>;
-    };
-    l2-intl-1@78200000 {
-      compatible = "l2-intl,carfield";
-      reg = <0x0 0x78200000 0x0 0x100000>;
-    };
-    l2-cont-1@78300000 {
-      compatible = "l2-cont,carfield";
-      reg = <0x0 0x78300000 0x0 0x100000>;
-    };
-    safety-island@60000000 {
-      compatible = "safety-island,carfield";
-      reg = <0x0 0x60000000 0x0 0x800000>;
-    };
-    integer-cluster@50000000 {
-      compatible = "integer-cluster,carfield";
-      reg = <0x0 0x50000000 0x0 0x800000>;
-    };
-    spatz-cluster@51000000 {
-      compatible = "spatz-cluster,carfield";
-      reg = <0x0 0x51000000 0x0 0x800000>;
-    };
-  };
-};
+
+  /include/ "carfield_soc.dtsi"
+
+};

sw/boot/carfield_bd_vcu118.dts

@@ -0,0 +1,8 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Cyril Koenig <[email protected]>
+
+
+/include/ "carfield.dtsi"

sw/boot/carfield_bd_vcu128.dts

@@ -45,8 +45,8 @@
     // interrupt and mac_irq
     interrupts-extended = <&PLIC0 19 &PLIC0 24>;
     //local-mac-address = [ 00 0A 35 04 E1 60 ]; // hero-vcu128-01
-    local-mac-address = [ 00 0A 35 04 E1 52 ]; // hero-vcu128-02
-    mac-address = [ 00 0A 35 04 E1 52 ];
+    local-mac-address = [ 00 0A 35 07 D5 DD ]; // hero-vcu128-03
+    mac-address = [ 00 0A 35 07 D5 DD ];
     device_type = "network";
     axistream-connected = <&eth_dma0>;
     axistream-control-connected = <&eth_dma0>;

sw/boot/carfield_pcie.dts

@@ -0,0 +1,26 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Cyril Koenig <[email protected]>
+
+/dts-v1/;
+/plugin/;
+&{/dev@0,0} {
+  axi-bus {
+    #address-cells = <2>;
+    #size-cells = <2>;
+    compatible = "simple-bus";
+    ranges;
+
+    /include/ "carfield_soc.dtsi"
+
+  };
+};
+
+&soc {
+  pcie-axi-bar@180000000 {
+    compatible = "xlnx,pcie-axi-bar";
+    reg = <0x1 0x80000000 0x0 0x80000000>;
+  };
+};