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WIP: Directly boot pulp cluster
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@sermazz
sermazz committed Nov 11, 2024
1 parent 356d044 commit 4593e04
Showing 1 changed file with 4 additions and 4 deletions.
8 changes: 4 additions & 4 deletions hw/chimera_cluster.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -330,9 +330,9 @@ module chimera_cluster
.SHARED_ICACHE ( "ENABLED" ),
.DIRECT_MAPPED_FEATURE ( "DISABLED" ),
.L2_SIZE ( MemIslRegionEnd - MemIslRegionStart ),
.ROM_BOOT_ADDR ( 32'h1A000000 ), // ??? substitute with correct ones
.BOOT_ADDR ( 32'h1c008080 ), // ??? substitute with correct ones
.INSTR_RDATA_WIDTH ( 32 ), // ???
.ROM_BOOT_ADDR ( SnitchBootROMRegionStart ),
.BOOT_ADDR ( SnitchBootROMRegionStart ), // not used if en_sa_boot_i is always 1

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[verible-verilog-lint] hw/chimera_cluster.sv#L334 

Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]"  location:{path:"hw/chimera_cluster.sv"  range:{start:{line:334  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
.INSTR_RDATA_WIDTH ( 32 ),
.CLUST_FPU ( 1 ),
.CLUST_FP_DIVSQRT ( 1 ),
.CLUST_SHARED_FP ( 2 ),
Expand Down Expand Up @@ -377,7 +377,7 @@ module chimera_cluster
.async_cluster_events_rptr_o ( ), // ???
.async_cluster_events_data_i ( '0 ), // ???

.en_sa_boot_i ( s_cluster_en_sa_boot ), // ??? fix or disconnect
.en_sa_boot_i ( 1'b1 ), // directly boot
.test_mode_i ( 1'b0 ), // ??? fix or disconnect

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[verible-verilog-lint] hw/chimera_cluster.sv#L381 

Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]"  location:{path:"hw/chimera_cluster.sv"  range:{start:{line:381  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
.fetch_en_i ( s_cluster_fetch_en ), // ??? fix or disconnect

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[verible-verilog-lint] hw/chimera_cluster.sv#L382 

Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]"  location:{path:"hw/chimera_cluster.sv"  range:{start:{line:382  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
.eoc_o ( s_cluster_eoc ), // ??? fix or disconnect

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[verible-verilog-lint] hw/chimera_cluster.sv#L383 

Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]"  location:{path:"hw/chimera_cluster.sv"  range:{start:{line:383  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
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