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WIP: Fix numcores
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sermazz committed Dec 13, 2024
1 parent c1d2a44 commit 6497ded
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2 changes: 1 addition & 1 deletion hw/chimera_cluster.sv
Original file line number Diff line number Diff line change
Expand Up @@ -401,7 +401,7 @@ module chimera_cluster
.fetch_en_i ( fetch_en_q ), //TODO: WIP to test offload

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[verible-verilog-lint] hw/chimera_cluster.sv#L401

Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]"  location:{path:"hw/chimera_cluster.sv"  range:{start:{line:401  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
.eoc_o ( ), //TODO: WIP to test offload

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GitHub Actions / verible-verilog-lint

[verible-verilog-lint] hw/chimera_cluster.sv#L402

Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]"  location:{path:"hw/chimera_cluster.sv"  range:{start:{line:402  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
.busy_o ( ), //TODO: WIP to test offload

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GitHub Actions / verible-verilog-lint

[verible-verilog-lint] hw/chimera_cluster.sv#L403

Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]"  location:{path:"hw/chimera_cluster.sv"  range:{start:{line:403  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
.cluster_id_i ( hart_base_id_i ),
.cluster_id_i ( ClusterId ),

.async_data_master_aw_wptr_o ( async_cluster_to_soc_axi_bus.aw_wptr ),
.async_data_master_aw_rptr_i ( async_cluster_to_soc_axi_bus.aw_rptr ),
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2 changes: 1 addition & 1 deletion hw/chimera_pkg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ package chimera_pkg;

localparam cluster_config_t ChimeraClusterCfg = '{
hasWideMasterPort: {1'b1, 1'b1, 1'b1, 1'b1, 1'b1},
NrCores: {8'h9, 8'h9, 8'h9, 8'h9, 8'h9}
NrCores: {8'h8, 8'h8, 8'h8, 8'h8, 8'h8}
};

function automatic int _sumVector(byte_bt [iomsb(ExtClusters):0] vector, int vectorLen);
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2 changes: 1 addition & 1 deletion sw/tests/testClusterOffload.c
Original file line number Diff line number Diff line change
Expand Up @@ -66,7 +66,7 @@ int main() {
// }
// else
// {
int count = 10000;
volatile int count = 10000;
if(hartId==0)
{
asm volatile (
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