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User-defined boot of PULP Cluster from host core sw + tests #634

User-defined boot of PULP Cluster from host core sw + tests

User-defined boot of PULP Cluster from host core sw + tests #634

GitHub Actions / verible-verilog-lint failed Jan 30, 2025 in 0s

reviewdog [verible-verilog-lint] report

reported by reviewdog 🐶

Findings (17)

hw/include/pulp_soc_defines.sv|19 col 3| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/include/pulp_soc_defines.sv|42 col 7| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/chimera_cluster.sv|172 col 18| Localparam name does not match the naming convention defined by regex pattern: (([A-Z0-9]+[a-z0-9]*)+(_[0-9]+)?) [Style: constants] [parameter-name-style]
hw/chimera_cluster.sv|381 col 101| Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
hw/chimera_cluster.sv|383 col 101| Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
hw/chimera_cluster.sv|384 col 101| Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
hw/chimera_cluster.sv|385 col 101| Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
hw/include/pulp_interfaces.sv|13 col 11| Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]
hw/include/pulp_interfaces.sv|47 col 11| Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]
hw/include/pulp_interfaces.sv|49 col 14| Explicitly define a storage type for every parameter and localparam, (ID_WIDTH). [Style: constants] [explicit-parameter-storage-type]
hw/include/pulp_interfaces.sv|84 col 11| Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]
hw/include/pulp_interfaces.sv|171 col 11| Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]
hw/include/pulp_interfaces.sv|245 col 11| Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]
hw/include/pulp_interfaces.sv|247 col 14| Explicitly define a storage type for every parameter and localparam, (ID_WIDTH). [Style: constants] [explicit-parameter-storage-type]
hw/include/pulp_interfaces.sv|282 col 11| Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]
hw/include/pulp_interfaces.sv|321 col 11| Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]
hw/include/pulp_interfaces.sv|409 col 11| Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]

Filtered Findings (0)

Annotations

Check warning on line 19 in hw/include/pulp_soc_defines.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/include/pulp_soc_defines.sv#L19

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/include/pulp_soc_defines.sv"  range:{start:{line:19  column:3}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:19  column:3}  end:{line:20}}  text:" *\n"}

Check warning on line 42 in hw/include/pulp_soc_defines.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/include/pulp_soc_defines.sv#L42

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/include/pulp_soc_defines.sv"  range:{start:{line:42  column:7}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:42  column:7}  end:{line:43}}  text:"`endif\n"}

Check warning on line 172 in hw/chimera_cluster.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/chimera_cluster.sv#L172

Localparam name does not match the naming convention defined by regex pattern: (([A-Z0-9]+[a-z0-9]*)+(_[0-9]+)?) [Style: constants] [parameter-name-style]
Raw output
message:"Localparam name does not match the naming convention defined by regex pattern: (([A-Z0-9]+[a-z0-9]*)+(_[0-9]+)?) [Style: constants] [parameter-name-style]"  location:{path:"hw/chimera_cluster.sv"  range:{start:{line:172  column:18}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}

Check warning on line 381 in hw/chimera_cluster.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/chimera_cluster.sv#L381

Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]"  location:{path:"hw/chimera_cluster.sv"  range:{start:{line:381  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}

Check warning on line 383 in hw/chimera_cluster.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/chimera_cluster.sv#L383

Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]"  location:{path:"hw/chimera_cluster.sv"  range:{start:{line:383  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}

Check warning on line 384 in hw/chimera_cluster.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/chimera_cluster.sv#L384

Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]"  location:{path:"hw/chimera_cluster.sv"  range:{start:{line:384  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}

Check warning on line 385 in hw/chimera_cluster.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/chimera_cluster.sv#L385

Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]"  location:{path:"hw/chimera_cluster.sv"  range:{start:{line:385  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}

Check warning on line 13 in hw/include/pulp_interfaces.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/include/pulp_interfaces.sv#L13

Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]
Raw output
message:"Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]"  location:{path:"hw/include/pulp_interfaces.sv"  range:{start:{line:13  column:11}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}

Check warning on line 47 in hw/include/pulp_interfaces.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/include/pulp_interfaces.sv#L47

Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]
Raw output
message:"Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]"  location:{path:"hw/include/pulp_interfaces.sv"  range:{start:{line:47  column:11}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}

Check warning on line 49 in hw/include/pulp_interfaces.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/include/pulp_interfaces.sv#L49

Explicitly define a storage type for every parameter and localparam, (ID_WIDTH). [Style: constants] [explicit-parameter-storage-type]
Raw output
message:"Explicitly define a storage type for every parameter and localparam, (ID_WIDTH). [Style: constants] [explicit-parameter-storage-type]"  location:{path:"hw/include/pulp_interfaces.sv"  range:{start:{line:49  column:14}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}

Check warning on line 84 in hw/include/pulp_interfaces.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/include/pulp_interfaces.sv#L84

Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]
Raw output
message:"Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]"  location:{path:"hw/include/pulp_interfaces.sv"  range:{start:{line:84  column:11}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}

Check warning on line 171 in hw/include/pulp_interfaces.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/include/pulp_interfaces.sv#L171

Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]
Raw output
message:"Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]"  location:{path:"hw/include/pulp_interfaces.sv"  range:{start:{line:171  column:11}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}

Check warning on line 245 in hw/include/pulp_interfaces.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/include/pulp_interfaces.sv#L245

Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]
Raw output
message:"Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]"  location:{path:"hw/include/pulp_interfaces.sv"  range:{start:{line:245  column:11}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}

Check warning on line 247 in hw/include/pulp_interfaces.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/include/pulp_interfaces.sv#L247

Explicitly define a storage type for every parameter and localparam, (ID_WIDTH). [Style: constants] [explicit-parameter-storage-type]
Raw output
message:"Explicitly define a storage type for every parameter and localparam, (ID_WIDTH). [Style: constants] [explicit-parameter-storage-type]"  location:{path:"hw/include/pulp_interfaces.sv"  range:{start:{line:247  column:14}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}

Check warning on line 282 in hw/include/pulp_interfaces.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/include/pulp_interfaces.sv#L282

Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]
Raw output
message:"Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]"  location:{path:"hw/include/pulp_interfaces.sv"  range:{start:{line:282  column:11}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}

Check warning on line 321 in hw/include/pulp_interfaces.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/include/pulp_interfaces.sv#L321

Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]
Raw output
message:"Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]"  location:{path:"hw/include/pulp_interfaces.sv"  range:{start:{line:321  column:11}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}

Check warning on line 409 in hw/include/pulp_interfaces.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/include/pulp_interfaces.sv#L409

Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]
Raw output
message:"Interface name does not match the naming convention defined by regex pattern: [a-z_0-9]+(_if) [Style: interface-conventions] [interface-name-style]"  location:{path:"hw/include/pulp_interfaces.sv"  range:{start:{line:409  column:11}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}