[config] Change configuration flag for FPU

config/config.mk

@@ -69,8 +69,8 @@ xqueue_size ?= 0
 # Enable the XpulpIMG extension
 xpulpimg ?= 1
 
-# FPU is deactivated by default
-zfinx_rv ?= 1
+# Enable FPU extensions
+zfinx ?= 1
 
 # DivSqrt deactivated by default
 xDivSqrt ?= 0

hardware/Makefile

@@ -93,7 +93,7 @@ vlog_defs += -DL2_BASE=32\'d$(l2_base) -DL2_SIZE=32\'d$(l2_size) -DL2_BANKS=$(l2
 vlog_defs += -DL1_BANK_SIZE=$(l1_bank_size)
 vlog_defs += -DBOOT_ADDR=32\'d$(boot_addr)
 vlog_defs += -DXPULPIMG=$(xpulpimg)
-vlog_defs += -DZFINX_RV=$(zfinx_rv)
+vlog_defs += -DZFINX=$(zfinx)
 vlog_defs += -DXDIVSQRT=$(xDivSqrt)
 vlog_defs += -DSNITCH_TRACE=$(snitch_trace)
 vlog_defs += -DAXI_DATA_WIDTH=$(axi_data_width)

hardware/deps/snitch/src/snitch.sv

@@ -94,7 +94,7 @@ module snitch
 );
 
   localparam int RegWidth = RVE ? 4 : 5;
-  localparam int RegNrReadPorts = ((snitch_pkg::XPULPIMG) || (snitch_pkg::ZFINX_RV)) ? 3 : 2;
+  localparam int RegNrReadPorts = ((snitch_pkg::XPULPIMG) || (snitch_pkg::ZFINX)) ? 3 : 2;
   localparam logic [RegWidth-1:0] SP = 2;
   localparam int OutstandingWfi = 8;
 
@@ -325,7 +325,7 @@ module snitch
   assign rd = inst_data_i[7 + RegWidth - 1:7];
   assign rs1 = inst_data_i[15 + RegWidth - 1:15];
   assign rs2 = inst_data_i[20 + RegWidth - 1:20];
-  assign rs3 = (((acc_qaddr_o == snitch_pkg::FP_SS) || (acc_qaddr_o == snitch_pkg::FP_DIVSQRT)) & (snitch_pkg::ZFINX_RV)) ? inst_data_i[27 + RegWidth - 1:27] :
+  assign rs3 = (((acc_qaddr_o == snitch_pkg::FP_SS) || (acc_qaddr_o == snitch_pkg::FP_DIVSQRT)) & (snitch_pkg::ZFINX)) ? inst_data_i[27 + RegWidth - 1:27] :
                ((acc_qaddr_o == snitch_pkg::XPULP_IPU) & (snitch_pkg::XPULPIMG)) ? inst_data_i[7 + RegWidth - 1:7] : '0;
 
   always_comb begin
@@ -821,7 +821,7 @@ module snitch
       end
 
       /////////////////////////
-      /* Zfinx_rv extensions */
+      /* ZFINX extensions */
       /////////////////////////
 
       /////////////////////////////////////
@@ -834,7 +834,7 @@ module snitch
       riscv_instr::FSGNJX_S,
       riscv_instr::FMIN_S,
       riscv_instr::FMAX_S: begin
-        if (snitch_pkg::ZFINX_RV) begin
+        if (snitch_pkg::ZFINX) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -848,7 +848,7 @@ module snitch
       end
       riscv_instr::FDIV_S,
       riscv_instr::FSQRT_S: begin
-        if (snitch_pkg::ZFINX_RV && snitch_pkg::XDivSqrt) begin
+        if (snitch_pkg::ZFINX && snitch_pkg::XDivSqrt) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -870,7 +870,7 @@ module snitch
       riscv_instr::FCVT_S_W,
       riscv_instr::FCVT_S_WU,
       riscv_instr::FMV_W_X: begin
-        if (snitch_pkg::ZFINX_RV) begin
+        if (snitch_pkg::ZFINX) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -886,7 +886,7 @@ module snitch
       riscv_instr::FMSUB_S,
       riscv_instr::FNMSUB_S,
       riscv_instr::FNMADD_S: begin
-        if (snitch_pkg::ZFINX_RV) begin
+        if (snitch_pkg::ZFINX) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -909,7 +909,7 @@ module snitch
       riscv_instr::FSGNJX_H,
       riscv_instr::FMIN_H,
       riscv_instr::FMAX_H: begin
-        if (snitch_pkg::ZFINX_RV && snitch_pkg::XF16) begin
+        if (snitch_pkg::ZFINX && snitch_pkg::XF16) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -923,7 +923,7 @@ module snitch
       end
       riscv_instr::FDIV_H,
       riscv_instr::FSQRT_H: begin
-        if (snitch_pkg::ZFINX_RV && snitch_pkg::XDivSqrt && snitch_pkg::XF16) begin
+        if (snitch_pkg::ZFINX && snitch_pkg::XDivSqrt && snitch_pkg::XF16) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -947,7 +947,7 @@ module snitch
       riscv_instr::FCVT_H_W,
       riscv_instr::FCVT_H_WU,
       riscv_instr::FMV_H_X: begin
-        if (snitch_pkg::ZFINX_RV && snitch_pkg::XF16) begin
+        if (snitch_pkg::ZFINX && snitch_pkg::XF16) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -963,7 +963,7 @@ module snitch
       riscv_instr::FMSUB_H,
       riscv_instr::FNMSUB_H,
       riscv_instr::FNMADD_H: begin
-        if (snitch_pkg::ZFINX_RV && snitch_pkg::XF16) begin
+        if (snitch_pkg::ZFINX && snitch_pkg::XF16) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -995,7 +995,7 @@ module snitch
       riscv_instr::VFSGNJN_R_H,
       riscv_instr::VFSGNJX_H,
       riscv_instr::VFSGNJX_R_H: begin
-        if (snitch_pkg::ZFINX_RV && snitch_pkg::XFVEC) begin
+        if (snitch_pkg::ZFINX && snitch_pkg::XFVEC) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -1010,7 +1010,7 @@ module snitch
       riscv_instr::VFDIV_H,
       riscv_instr::VFDIV_R_H,
       riscv_instr::VFSQRT_H: begin
-        if (snitch_pkg::ZFINX_RV && snitch_pkg::XDivSqrt && snitch_pkg::XFVEC) begin
+        if (snitch_pkg::ZFINX && snitch_pkg::XDivSqrt && snitch_pkg::XFVEC) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -1044,7 +1044,7 @@ module snitch
       riscv_instr::VFCVT_XU_H,
       riscv_instr::VFCVT_H_X,
       riscv_instr::VFCVT_H_XU: begin
-        if (snitch_pkg::ZFINX_RV && snitch_pkg::XFVEC) begin
+        if (snitch_pkg::ZFINX && snitch_pkg::XFVEC) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -1060,7 +1060,7 @@ module snitch
       riscv_instr::VFMAC_R_H,
       riscv_instr::VFMRE_H,
       riscv_instr::VFMRE_R_H: begin
-        if (snitch_pkg::ZFINX_RV && snitch_pkg::XFVEC) begin
+        if (snitch_pkg::ZFINX && snitch_pkg::XFVEC) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -1075,7 +1075,7 @@ module snitch
       end
       riscv_instr::VFCPKA_H_S,
       riscv_instr::VFCPKB_H_S: begin
-        if (snitch_pkg::ZFINX_RV && snitch_pkg::XFVEC) begin
+        if (snitch_pkg::ZFINX && snitch_pkg::XFVEC) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -1095,7 +1095,7 @@ module snitch
       riscv_instr::VFNDOTPEX_S_R_H,
       riscv_instr::VFSUMEX_S_H,
       riscv_instr::VFNSUMEX_S_H: begin
-        if (snitch_pkg::ZFINX_RV && snitch_pkg::XFVEC) begin
+        if (snitch_pkg::ZFINX && snitch_pkg::XFVEC) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -1113,7 +1113,7 @@ module snitch
       riscv_instr::FCNDOTPEX_S_H,
       riscv_instr::FCCDOTPEX_S_H,
       riscv_instr::FCCNDOTPEX_S_H: begin
-        if (snitch_pkg::ZFINX_RV && snitch_pkg::XFVEC) begin
+        if (snitch_pkg::ZFINX && snitch_pkg::XFVEC) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -1136,7 +1136,7 @@ module snitch
       riscv_instr::FSGNJX_B,
       riscv_instr::FMIN_B,
       riscv_instr::FMAX_B: begin
-        if (snitch_pkg::ZFINX_RV && snitch_pkg::XF8) begin
+        if (snitch_pkg::ZFINX && snitch_pkg::XF8) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -1150,7 +1150,7 @@ module snitch
       end
       riscv_instr::FDIV_B,
       riscv_instr::FSQRT_B: begin
-        if (snitch_pkg::ZFINX_RV && snitch_pkg::XDivSqrt && snitch_pkg::XF8) begin
+        if (snitch_pkg::ZFINX && snitch_pkg::XDivSqrt && snitch_pkg::XF8) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -1175,7 +1175,7 @@ module snitch
       riscv_instr::FCLASS_B,
       riscv_instr::FCVT_B_W,
       riscv_instr::FCVT_B_WU: begin
-        if (snitch_pkg::ZFINX_RV && snitch_pkg::XF8) begin
+        if (snitch_pkg::ZFINX && snitch_pkg::XF8) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -1191,7 +1191,7 @@ module snitch
       riscv_instr::FMSUB_B,
       riscv_instr::FNMSUB_B,
       riscv_instr::FNMADD_B: begin
-        if (snitch_pkg::ZFINX_RV && snitch_pkg::XF8) begin
+        if (snitch_pkg::ZFINX && snitch_pkg::XF8) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -1223,7 +1223,7 @@ module snitch
       riscv_instr::VFSGNJN_R_B,
       riscv_instr::VFSGNJX_B,
       riscv_instr::VFSGNJX_R_B: begin
-        if (snitch_pkg::ZFINX_RV && snitch_pkg::XFVEC) begin
+        if (snitch_pkg::ZFINX && snitch_pkg::XFVEC) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -1238,7 +1238,7 @@ module snitch
       riscv_instr::VFDIV_B,
       riscv_instr::VFDIV_R_B,
       riscv_instr::VFSQRT_B: begin
-        if (snitch_pkg::ZFINX_RV && snitch_pkg::XDivSqrt && snitch_pkg::XFVEC) begin
+        if (snitch_pkg::ZFINX && snitch_pkg::XDivSqrt && snitch_pkg::XFVEC) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -1274,7 +1274,7 @@ module snitch
       riscv_instr::VFCVT_XU_B,
       riscv_instr::VFCVT_B_X,
       riscv_instr::VFCVT_B_XU: begin
-        if (snitch_pkg::ZFINX_RV && snitch_pkg::XFVEC) begin
+        if (snitch_pkg::ZFINX && snitch_pkg::XFVEC) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -1290,7 +1290,7 @@ module snitch
       riscv_instr::VFMAC_R_B,
       riscv_instr::VFMRE_B,
       riscv_instr::VFMRE_R_B: begin
-        if (snitch_pkg::ZFINX_RV && snitch_pkg::XFVEC) begin
+        if (snitch_pkg::ZFINX && snitch_pkg::XFVEC) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -1305,7 +1305,7 @@ module snitch
       end
       riscv_instr::VFCPKA_B_S,
       riscv_instr::VFCPKB_B_S: begin
-        if (snitch_pkg::ZFINX_RV && snitch_pkg::XFVEC) begin
+        if (snitch_pkg::ZFINX && snitch_pkg::XFVEC) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -1325,7 +1325,7 @@ module snitch
       riscv_instr::VFNDOTPEX_H_R_B,
       riscv_instr::VFSUMEX_H_B,
       riscv_instr::VFNSUMEX_H_B: begin
-        if (snitch_pkg::ZFINX_RV && snitch_pkg::XFVEC) begin
+        if (snitch_pkg::ZFINX && snitch_pkg::XFVEC) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -1342,7 +1342,7 @@ module snitch
       riscv_instr::VFDOTPEXB_S_B,
       riscv_instr::VFDOTPEXA_S_R_B,
       riscv_instr::VFDOTPEXB_S_R_B: begin
-        if (snitch_pkg::ZFINX_RV && snitch_pkg::XFVEC) begin
+        if (snitch_pkg::ZFINX && snitch_pkg::XFVEC) begin
           write_rd = 1'b0;
           uses_rd = 1'b1;
           acc_qvalid_o = valid_instr;
@@ -2025,19 +2025,19 @@ module snitch
 
         // F/D Extension
         riscv_instr::CSR_FFLAGS: begin
-          if (snitch_pkg::ZFINX_RV) begin
+          if (snitch_pkg::ZFINX) begin
             csr_rvalue = {27'b0, fcsr_q.fflags};
             fcsr_d.fflags = fpnew_pkg::status_t'(alu_result[4:0]);
           end else illegal_csr = 1'b1;
         end
         riscv_instr::CSR_FRM: begin
-          if (snitch_pkg::ZFINX_RV) begin
+          if (snitch_pkg::ZFINX) begin
             csr_rvalue = {29'b0, fcsr_q.frm};
             fcsr_d.frm = fpnew_pkg::roundmode_e'(alu_result[2:0]);
           end else illegal_csr = 1'b1;
         end
         riscv_instr::CSR_FCSR: begin
-          if (snitch_pkg::ZFINX_RV) begin
+          if (snitch_pkg::ZFINX) begin
             csr_rvalue = {24'b0, fcsr_q};
             fcsr_d = fcsr_t'(alu_result[7:0]);
           end else illegal_csr = 1'b1;
@@ -2114,7 +2114,7 @@ module snitch
     endcase
   end
 
-  if ((snitch_pkg::ZFINX_RV) | (snitch_pkg::XPULPIMG)) begin
+  if ((snitch_pkg::ZFINX) | (snitch_pkg::XPULPIMG)) begin
     always_comb begin
       unique case (opc_select)
         None: opc = '0;
@@ -2131,8 +2131,8 @@ module snitch
   assign gpr_raddr[1] = rs2;
   // connect third read port only if present
   if (RegNrReadPorts >= 3) begin : gpr_raddr_2
-    assign gpr_raddr[2] = ((snitch_pkg::ZFINX_RV) || (snitch_pkg::XPULPIMG) && (opc_select == RegRd)) ? rd  :
-                          ((snitch_pkg::ZFINX_RV) || (snitch_pkg::XPULPIMG) && (opc_select == Reg))   ? rs3 : '0;
+    assign gpr_raddr[2] = ((snitch_pkg::ZFINX) || (snitch_pkg::XPULPIMG) && (opc_select == RegRd)) ? rd  :
+                          ((snitch_pkg::ZFINX) || (snitch_pkg::XPULPIMG) && (opc_select == Reg))   ? rs3 : '0;
   end
 
   // --------------------

hardware/deps/snitch/src/snitch_pkg.sv

@@ -15,8 +15,8 @@ package snitch_pkg;
   localparam MetaIdWidth                = idx_width(NumIntOutstandingLoads);
   // Xpulpimg extension enabled?
   localparam bit XPULPIMG = `ifdef XPULPIMG `XPULPIMG `else 1'bX `endif;
-  // Zfinx_rv extension enabled?
-  localparam bit ZFINX_RV = `ifdef ZFINX_RV `ZFINX_RV `else 1'bX `endif;
+  // ZFINX extension enabled?
+  localparam bit ZFINX = `ifdef ZFINX `ZFINX `else 1'bX `endif;
   // XDivSqrt extension enabled?
   localparam bit XDIVSQRT = `ifdef XDIVSQRT `XDIVSQRT `else 1'bX `endif;
 

software/riscv-tests/isa/snitch_isa.mk

@@ -110,7 +110,7 @@ endif
 endif
 
 ifeq ($(COMPILER), llvm)
-ifeq ($(zfinx_rv),1)
+ifeq ($(zfinx),1)
 
 	rv32uzfinx_snitch_sc_tests = \
 		fadd \

software/runtime/runtime.mk

@@ -24,7 +24,7 @@ OMP_DIR            ?= $(ROOT_DIR)/omp
 
 COMPILER      ?= gcc
 XPULPIMG      ?= $(xpulpimg)
-ZFINX_RV      ?= $(zfinx_rv)
+ZFINX      		?= $(zfinx)
 
 RISCV_XLEN    ?= 32
 
@@ -54,7 +54,7 @@ else
 	# Use LLVM by default
 	# LLVM compiler -march
 	RISCV_ARCH ?= rv$(RISCV_XLEN)ima
-	ifeq ($(ZFINX_RV), 1)
+	ifeq ($(ZFINX), 1)
 		RISCV_ARCH := $(RISCV_ARCH)_zfinx
 		RISCV_ARCH := $(RISCV_ARCH)_zhinx
 		RISCV_ARCH := $(RISCV_ARCH)_zquarterinx