[DRAMsys 2.0] Terapool DRAMsys Merge Request#93

Closed

yichao-zh wants to merge 45 commits intomainfrom terapool_DRAM_RTL

+689-78

Commits on Mar 20, 2024

Commits on Mar 22, 2024

[DRAMsys] Remove the local version of DRAMsys hardware folder, add the open-sourced DRAMsys as a submodule
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[Config] Move the dram related configurations to the config.mk
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[Makefile] Modify Makefile for updating submodule, patching dram configurations, and compiling dramsys dynamic library.
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[hardware] hardware change for the new version dramsys support
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[DRAM] Add the configuration files for HBM2 DRAM simulation, these file will patch to dram_sim_rtl submodule by makefile target
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[tb] Change back the simulation clk period to 2ns, but 1ns will have better DRAM BW as the HBM2 support upto 3600Gbps DDR
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[Bender] Update bender to the correct RTL name, as DRAMsys updated themself
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[software] Update memcpy kernel with reasonable transfer size and turn on the verification
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[config] Change simulation to SRAM as L2 for CI checking
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[CI test] Fix tb whitespace tailing and change the bender to compile dramsys rtl only by vsim
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[CHANGELOG and README] Add changelog and readme for DRAM co-simulation
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