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Getting stated

Clone the repo and move to questa_sim directory inside the sim directory.

cd sim/questa_sim

To compile

make compile

To simulate

make simulate test=<test_name> uvm_verbosity=<uvm_verbosity>

To run regression

make regression testlist_name=<testlist_name>

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  • SystemVerilog 78.3%
  • Verilog 12.9%
  • Makefile 7.2%
  • Python 1.1%
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