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Merge pull request #781 from rdaly525/patch-verilog-inouts
Repull of #777
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Original file line number | Diff line number | Diff line change |
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@@ -1,55 +1,60 @@ | ||
#ifndef COREIR_VERILOG_HPP_ | ||
#define COREIR_VERILOG_HPP_ | ||
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#include <memory> | ||
#include <ostream> | ||
#include "coreir.h" | ||
#include "verilogAST.hpp" | ||
#include <memory> | ||
#include <ostream> | ||
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namespace vAST = verilogAST; | ||
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namespace CoreIR { | ||
namespace Passes { | ||
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class Verilog : public InstanceGraphPass { | ||
bool _inline = false; | ||
bool verilator_debug = true; | ||
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// We store a vector of module name, module AST node pairs to support | ||
// serializing to a single or multiple files | ||
std::vector<std::pair<std::string, std::unique_ptr<vAST::AbstractModule>>> | ||
modules; | ||
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// Externally defined modules (no moduleDef), for now we just emit comments | ||
// listing them when compiling to a single file | ||
std::vector<Module*> extern_modules; | ||
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// Set used to track generators that are compiled as parametrized verilog | ||
// modules. These parametrized modules have been instanced to create coreir | ||
// modules, but we only need to compile the verilog definition once | ||
std::set<Generator*> verilog_generators_seen; | ||
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void compileModule(Module* module); | ||
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public: | ||
static std::string ID; | ||
Verilog() : InstanceGraphPass(ID, "Compiles IR to Verilog files", true) {} | ||
~Verilog(){}; | ||
bool runOnInstanceGraphNode(InstanceGraphNode& node) override; | ||
void initialize(int argc, char** argv) override; | ||
void setAnalysisInfo() override { | ||
onlyTop = true; | ||
addDependency( | ||
"verifyconnectivity --onlyinputs"); // Should change back to check | ||
// all connections | ||
addDependency("verifyflattenedtypes"); | ||
} | ||
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void writeToStream(std::ostream& os); | ||
void writeToFiles(const std::string& dir, | ||
std::unique_ptr<std::string> product_file); | ||
bool _inline = false; | ||
bool verilator_debug = false; | ||
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// We store a vector of module name, module AST node pairs to support | ||
// serializing to a single or multiple files | ||
std::vector<std::pair<std::string, std::unique_ptr<vAST::AbstractModule>>> | ||
modules; | ||
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// Externally defined modules (no moduleDef), for now we just emit comments | ||
// listing them when compiling to a single file | ||
std::vector<Module *> extern_modules; | ||
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// Set used to track generators that are compiled as parametrized verilog | ||
// modules. These parametrized modules have been instanced to create coreir | ||
// modules, but we only need to compile the verilog definition once | ||
std::set<Generator *> verilog_generators_seen; | ||
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void compileModule(Module *module); | ||
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std::vector<std::unique_ptr<vAST::AbstractPort>> | ||
compilePorts(RecordType *record_type); | ||
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std::unique_ptr<vAST::AbstractModule> | ||
compileStringBodyModule(json verilog_json, std::string name, Module *module); | ||
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public: | ||
static std::string ID; | ||
Verilog() : InstanceGraphPass(ID, "Compiles IR to Verilog files", true) {} | ||
~Verilog(){}; | ||
bool runOnInstanceGraphNode(InstanceGraphNode &node) override; | ||
void initialize(int argc, char **argv) override; | ||
void setAnalysisInfo() override { | ||
onlyTop = true; | ||
addDependency("verifyconnectivity --onlyinputs"); // Should change back to | ||
// check all connections | ||
addDependency("verifyflattenedtypes"); | ||
} | ||
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void writeToStream(std::ostream &os); | ||
void writeToFiles(const std::string &dir, | ||
std::unique_ptr<std::string> product_file); | ||
}; | ||
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} // namespace Passes | ||
} // namespace CoreIR | ||
} // namespace Passes | ||
} // namespace CoreIR | ||
#endif |
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Original file line number | Diff line number | Diff line change |
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@@ -1,12 +1,18 @@ | ||
// This is an important comment for foo!! | ||
module foo (input I, output O); | ||
module foo (input I, inout IO, output O); | ||
assign O = I; | ||
assign IO = I; | ||
endmodule | ||
module top (input I, output O); | ||
module top (input I, inout IO0, inout IO1, output O); | ||
wire inst0_IO; | ||
wire inst0_O; | ||
wire inst1_IO; | ||
wire inst1_O; | ||
foo inst0(.I(I), .O(inst0_O)); | ||
foo inst1(.I(inst0_O), .O(inst1_O)); | ||
foo inst0(.I(I), .IO(inst0_IO), .O(inst0_O)); | ||
foo inst1(.I(inst0_O), .IO(inst1_IO), .O(inst1_O)); | ||
assign O = inst1_O; | ||
assign inst0_IO = inst1_IO; | ||
assign IO0 = inst0_IO; | ||
assign inst0_IO = IO1; | ||
endmodule | ||
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