target/riscv: Implement ability to re-examine target #1020
Conversation
r->wp_triggers_negative_cache should be NULL after free to avoid issues connected with multiple sequential calls of free_wp_triggers_cache() Change-Id: Ib39fe0c9dcd01b6e78021bf86a34f3888e94b1d5 Signed-off-by: Kirill Radkin <[email protected]>
Add a new OpenOCD command `re_examine` to enforce re-examination of target. Some of existing hardware have a writable misa.V bit. It means that it can be enabled by software. We need an opportunity to enforce examine procedure in OpenOCD to query the capabilities of the target. Change-Id: Id523315486f416c28021199e29f53242d1a37069 Signed-off-by: Kirill Radkin <[email protected]>
kr-sc
force-pushed
the
kr-sc/re-examine-command
branch
from
085e80b to
0dba65f
Compare
| @@ -11515,6 +11515,13 @@ riscv exec_progbuf 0x0330000f 0x0000100f | |||
| riscv exec_progbuf 0x94a20405 | |||
| @end example | |||
|
|
|||
| @subsection RISC-V Syntacore hardware-specific Commands | |||
There was a problem hiding this comment.
I would not call this a Syntacore hardware-specific command.
Spike also has the ability to change at runtime which extensions are implemented. The RISC-V specification does allow the ISA to change at runtime if the hardware supports it.
There was a problem hiding this comment.
I would not call this a Syntacore hardware-specific command.
This is a mistake on our side. This code was in Syntacore codebase for a while and we just missed that this part had to be re-written during internal review.
| { | ||
| target->examined = false; | ||
| } | ||
|
|
There was a problem hiding this comment.
I am not sure if touching target.h/c is the best approach.
Myself, I would open a patch on the upsteam OpenOCD changing the visibility of this function.
For now, I would set the target->examined = false directly in the handle_re_examine_target() and add a // TODO to change it later.
| RISCV_INFO(r); | ||
|
|
||
| if (target->watchpoints || target->breakpoints) { | ||
| LOG_TARGET_ERROR(target, "Please, remove all breakpoints and watchpoints."); |
There was a problem hiding this comment.
I would change the message, something akin to: "Re-examination requires the removal of all breakpoints and watchpoints."
|
NOTE: @MarekVCodasip Kirill will be out for a while... This patch won't get any updates because of this for some time. Likely, we'll refactor the patch a little bit and re-upload it again. In any case - thanks for review, the suggested changes will be integrated. |
Add a new OpenOCD command
re_examineto enforce re-examination of target. Some of existing hardware have a writable misa.V bit. It means that it can be enabled by software. We need an opportunity to enforceexamineprocedure in OpenOCD to query the capabilities of the target.Also this patch includes commit with fix of a little issue connected with clearing triggers cache.