target/riscv: set VLENB/MTOPI/MTOPEI existence on 0.11 targets

[en-sc]

commit 5f45b5b ("target/riscv: reg cache entry is initialized before access") introduced an assertion in riscv_reg_impl_gdb_regno_exist().
Link:

riscv-openocd/src/target/riscv/riscv_reg.c

Lines 385 to 389 in f82c5a7

	assert(false
	&& "Existence of other registers is determined "
	"depending on existence of these ones, so "
	"whether these register exist or not should be "
	"set explicitly.");

This assertion fails on RISC-V Debug Spec. 0.11 targets. The commit is intended to fix this.

Change-Id: I20b56df1517f4071f4b6e39c83178a29a9cf95b0

[aap-sc]

LGTM, review internally.

[MarekVCodasip]

Ran riscv-tests on the hifive1-reva board we have. These are the results:

:::::::::::::::::::::::::::[ ran 73 tests in 220s ]:::::::::::::::::::::::::::
19 tests returned not_applicable
42 tests returned pass
4 tests returned exception
   DebugFunctionCall > logs/20250123-175903-HiFive1-DebugFunctionCall.log
   IcountTest > logs/20250123-175928-HiFive1-IcountTest.log
   MemTestReadInvalid > logs/20250123-180059-HiFive1-MemTestReadInvalid.log
   RepeatReadTest > logs/20250123-180132-HiFive1-RepeatReadTest.log
8 tests returned fail
   EtriggerTest > logs/20250123-175917-HiFive1-EtriggerTest.log
   InstantHaltTest > logs/20250123-180013-HiFive1-InstantHaltTest.log
   InterruptTest > logs/20250123-180015-HiFive1-InterruptTest.log
   ItriggerTest > logs/20250123-180041-HiFive1-ItriggerTest.log
   MemorySampleMixed > logs/20250123-180101-HiFive1-MemorySampleMixed.log
   MemorySampleSingle > logs/20250123-180109-HiFive1-MemorySampleSingle.log
   Semihosting > logs/20250123-180134-HiFive1-Semihosting.log
   SemihostingFileio > logs/20250123-180137-HiFive1-SemihostingFileio.log

[MarekVCodasip]

Not a huge fan of this solution, but I don't see any other way which does not interfere in the regular 0.13 target.

Please, add the comments I suggested to ensure that future readers know.