Initial commit of Hummingbirdv2

.gitignore

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+riscv-tools/prebuilt_tools/prefix/*

LICENSE

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+
                                  Apache License
                            Version 2.0, January 2004
                         http://www.apache.org/licenses/

README.md

@@ -1,2 +1,71 @@
-# e203_hbirdv2
-The Ultra-Low Power RISC Core
+Hummingbirdv2 E203 Core and SoC 
+===============================
+
+About
+-----
+
+This repository hosts the project for open-source Hummingbirdv2 E203 RISC-V processor Core and SoC, it's developped and opensourced by Nuclei(www.nucleisys.com), the leading RISC-V IP and Solution company based on China Mainland.
+
+This's an upgraded version of the project Hummingbird E203 maintained in SI-RISCV/e200_opensource(https://github.com/SI-RISCV/e200_opensource), so we call it Hummingbirdv2 E203, and its architecture is shown in the figure below.
+![hbirdv2](pics/hbirdv2_soc.JPG)
+
+
+In this new version, we have following updates.
+* Add NICE(Nuclei Instruction Co-unit Extension) for E203 core, so user could create customized HW co-units with E203 core easily.
+* Integrate the APB interface peripherals(GPIO, I2C, UART, SPI, PWM) from PULP Platform(https://github.com/pulp-platform) into Hummingbirdv2 SoC, these peripherals are implemented in System Verilog language, so it's easy for user to understand. 
+* Add new development board(DDR200T) support for Hummingbirdv2 SoC. 
+
+Welcome to visit https://www.rvmcu.com/community-community.html to participate in the discussion of the Hummingbird E203.
+
+Welcome to visit http://www.rvmcu.com/ for more comprehensive information of availiable RISC-V MCU chips and embedded development. 
+
+
+Detailed Introduction and Quick Start-up
+----------------------------------------
+
+We have provided very detailed introduction and quick start-up documents to help you ramping it up. 
+
+The detailed introduction and the quick start documentation can be seen 
+from https://www.rvmcu.com/campus-campus.html.
+
+By following the guidences from the doc, you can very easily start to use Hummingbirdv2 E203 processor Core and SoC.
+
+What are you waiting for? Try it out now!
+
+Dedicated FPGA-Board and JTAG-Debugger 
+--------------------------------------
+In order to easy user to study RISC-V in a quick and easy way, we have made a dedicated FPGA-Board and JTAG-Debugger.  Diagram as below:
+
+#### 蜂鸟E203专用的FPGA开发板
+
+#### DDR200T 
+![DDR200T](pics/DDR200T.JPG)
+
+#### 蜂鸟E203专用的JTAG调试器
+![Debugger](pics/debugger.JPG)
+
+The detailed introduction and the relevant documentation can be seen from https://nucleisys.com/developboard.php.
+
+
+Release History
+-----------------------------
+#### Note at First:
+    -- Many people asked if this core and SoC can be commercially used, the answer as below:
+       * According to the Apache 2.0 license, this open-sourced core can be used in commercial way.
+       * But the feature is not full. 
+       * The main purpose of this open-sourced core is to be used by students/university/research/
+         and entry-level-beginners, hence, the commercial quality (bug-free) and service of this core
+         is not not not warranted!!! 
+
+#### Jul 28, 2020
+
+    -- This is release 0.1.1 of Hbirdv2.
+    -- NOTE:
+       This's an upgraded version of the project Hummingbird E203 maintained in SI-RISCV/e200_opensource
+       (https://github.com/SI-RISCV/e200_opensource), here are the new features of this release.
+       * Add NICE(Nuclei Instruction Co-unit Extension) for E203 core
+       * Integrate the APB interface peripherals(GPIO, I2C, UART, SPI, PWM) from PULP Platform
+       * Add new development board(DDR200T) support for Hummingbirdv2 SoC. 
+
+       
+

fpga/.gitignore

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+fpga_flist
+install
+vivado.*
+common.mk.real
+common.mk.github
+

fpga/Makefile

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+# See LICENSE for license details.
+base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
+FPGA_NAME := ddr200t
+FPGA_DIR := $(base_dir)/${FPGA_NAME}
+INSTALL_RTL ?= $(base_dir)/install/rtl
+
+include common.mk

fpga/README.md

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+Hummingbirdv2 E203 
+
+install RTL file and make .mcs file
+================
+
+
+For ddr200t:
+
+make install  FPGA_NAME=ddr200t 
+
+make mcs      FPGA_NAME=ddr200t 
+
+================
+

fpga/common.mk

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+# See LICENSE for license details.
+
+# Required variables:
+# - FPGA_DIR
+# - INSTALL_RTL
+
+CORE = e203
+PATCHVERILOG ?= ""
+
+
+
+base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
+
+
+
+# Install RTLs
+install: 
+	mkdir -p ${PWD}/install
+	cp ${PWD}/../rtl/${CORE} ${INSTALL_RTL} -rf
+	cp ${FPGA_DIR}/src/system.v ${INSTALL_RTL}/system.v -rf
+	sed -i '1i\`define FPGA_SOURCE\'  ${INSTALL_RTL}/core/${CORE}_defines.v
+
+EXTRA_FPGA_VSRCS := 
+verilog := $(wildcard ${INSTALL_RTL}/*/*.v)
+verilog += $(wildcard ${INSTALL_RTL}/*/*/*.sv)
+verilog += $(wildcard ${INSTALL_RTL}/*.v)
+
+
+# Build .mcs
+.PHONY: mcs
+mcs : install
+	BASEDIR=${base_dir} VSRCS="$(verilog)" EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) mcs
+
+
+# Build .bit
+.PHONY: bit
+bit : install
+	BASEDIR=${base_dir} VSRCS="$(verilog)" EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) bit
+
+
+.PHONY: setup
+setup: 
+	BASEDIR=${base_dir} VSRCS="$(verilog)" EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) setup
+
+
+
+
+
+# Clean
+.PHONY: clean
+clean:
+	$(MAKE) -C $(FPGA_DIR) clean
+	rm -rf fpga_flist
+	rm -rf install
+	rm -rf vivado.*
+	rm -rf novas.*
+

fpga/ddr200t/Makefile

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+VIVADO ?= vivado
+VIVADOFLAGS := \
+	-nojournal -mode batch \
+	-source script/board.tcl \
+	-source script/prologue.tcl
+
+VIVADOFLAGS_SETUP := \
+	-nojournal -mode gui \
+	-source script/board.tcl \
+	-source script/prologue_setup.tcl
+
+# Path to a program in raw binary format to be flashed into the address that the
+# bootrom jumps to.
+FLASHED_PROGRAM ?=
+
+bit := obj/system.bit
+$(bit): script/impl.tcl  script/init.tcl
+	VSRCS="$(VSRCS)" EXTRA_VSRCS="$(EXTRA_VSRCS)" $(VIVADO) $(VIVADOFLAGS) -source script/init.tcl -source script/impl.tcl
+
+.PHONY: bit
+bit: $(bit)
+
+mcs := obj/system.mcs
+$(mcs): $(bit)
+	$(VIVADO) $(VIVADOFLAGS) script/cfgmem.tcl -tclargs $@ $^ $(FLASHED_PROGRAM)
+
+.PHONY: mcs
+mcs: $(mcs)
+
+.PHONY: setup
+setup:
+	VSRCS="$(VSRCS)" EXTRA_VSRCS="$(EXTRA_VSRCS)" $(VIVADO) $(VIVADOFLAGS_SETUP) -source script/init_setup.tcl 
+
+
+.PHONY: clean
+clean::
+	rm -rf -- .Xil .ip_user_files *.os obj src/generated usage_statistics_webtalk.xml usage_statistics_webtalk.html *.log

fpga/ddr200t/constrs/nuclei-config.xdc

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+set_property -dict [list \
+  CONFIG_VOLTAGE {3.3} \
+  CFGBVS {VCCO} \
+  BITSTREAM.CONFIG.SPI_BUSWIDTH {4} \
+  ] [current_design]